198 lines
8.7 KiB
C
198 lines
8.7 KiB
C
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \author Daniele Basile <asterix@develer.com>
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*
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* AT91SAM7 Analog to Digital Converter.
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*
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*/
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#ifndef AT91_ADC_H
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#define AT91_ADC_H
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/**
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* ADC control register
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*/
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#define ADC_CR_OFF 0x00000000 ///< Control register offeset.
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#define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
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#define ADC_SWRST 0 ///< Software reset.
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#define ADC_START 1 ///< Start conversion.
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/**
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* ADC mode register
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*/
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#define ADC_MR_OFF 0x00000004 ///< Mode register offeset.
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#define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
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#define ADC_TRGEN 0 ///< Trigger enable.
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#define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
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#define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
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#define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
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#define ADC_TRGSEL_EXT 0x0000000C ///< External trigger.
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#define ADC_LOWRES 4 ///< Resolution 0: 10-bit, 1: 8-bit.
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#define ADC_SLEEP 5 ///< Sleep mode.
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/**
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* Prescaler rate selection.
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* ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
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*/
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#define ADC_PRESCALER_MASK 0x00003F00 ///< Prescaler rate selection mask.
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#define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift.
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/**
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* Start up timer.
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* Startup time = (ADC_STARTUP_VALUE + 1) * 8 /ADCClock
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*/
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#define ADC_STARTUP_MASK 0x001F0000 ///< Start up timer mask.
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#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
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/**
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* Sample & hold time.
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* Sample & hold time = (ADC_SHTIM_VALUE + 1) * 8 /ADCClock
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*/
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#define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask.
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#define ADC_SHTIME_SHIFT 24 ///< Sample & hold time shift.
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/**
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* ADC channel enable register
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*/
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#define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
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#define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address.
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/**
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* ADC channel disable register
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*/
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#define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
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#define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address.
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/**
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* ADC channel status register
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*/
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#define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
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#define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
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#define ADC_CH_MASK 0x000000FF ///< Channel mask.
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#define ADC_CH0 0 ///< Channel 0
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#define ADC_CH1 1 ///< Channel 1
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#define ADC_CH2 2 ///< Channel 2
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#define ADC_CH3 3 ///< Channel 3
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#define ADC_CH4 4 ///< Channel 4
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#define ADC_CH5 5 ///< Channel 5
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#define ADC_CH6 6 ///< Channel 6
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#define ADC_CH7 7 ///< Channel 7
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/**
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* ADC status register
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*/
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#define ADC_SR_OFF 0x0000001C ///< Status register offeset.
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#define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
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/**
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* ADC Interrupt enable register.
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*/
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#define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
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#define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register.
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/**
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* ADC Interrupt disable register.
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*/
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#define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
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#define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register.
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/**
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* ADC Interrupt mask register.
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*/
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#define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset.
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#define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register.
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#define ADC_EOC_MASK 0x000000FF ///< End of converison mask.
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#define ADC_EOC0 0 ///< End of conversion channel 0.
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#define ADC_EOC1 1 ///< End of conversion channel 1.
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#define ADC_EOC2 2 ///< End of conversion channel 2.
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#define ADC_EOC3 3 ///< End of conversion channel 3.
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#define ADC_EOC4 4 ///< End of conversion channel 4.
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#define ADC_EOC5 5 ///< End of conversion channel 5.
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#define ADC_EOC6 6 ///< End of conversion channel 6.
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#define ADC_EOC7 7 ///< End of conversion channel 7.
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#define ADC_OVRE0 8 ///< Overrun error channel 0.
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#define ADC_OVRE1 9 ///< Overrun error channel 1.
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#define ADC_OVRE2 10 ///< Overrun error channel 2.
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#define ADC_OVRE3 11 ///< Overrun error channel 3.
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#define ADC_OVRE4 12 ///< Overrun error channel 4.
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#define ADC_OVRE5 13 ///< Overrun error channel 5.
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#define ADC_OVRE6 14 ///< Overrun error channel 6.
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#define ADC_OVRE7 15 ///< Overrun error channel 7.
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#define ADC_DRDY 16 ///< Data ready.
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#define ADC_GOVRE 17 ///< General overrun error.
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#define ADC_ENDRX 18 ///< End of RX buffer.
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#define ADC_RXBUFF 19 ///< Rx buffer full.
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/**
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* ADC last convert data register.
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*/
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#define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
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#define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted data register.
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/**
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* ADC channel data register.
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*
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* \{
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*/
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#define ADC_CDR0_OFF 0x00000030 ///< Channel data register 0 offeset.
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#define ADC_CDR1_OFF 0x00000034 ///< Channel data register 1 offeset.
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#define ADC_CDR2_OFF 0x00000038 ///< Channel data register 2 offeset.
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#define ADC_CDR3_OFF 0x0000003C ///< Channel data register 3 offeset.
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#define ADC_CDR4_OFF 0x00000040 ///< Channel data register 4 offeset.
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#define ADC_CDR5_OFF 0x00000044 ///< Channel data register 5 offeset.
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#define ADC_CDR6_OFF 0x00000048 ///< Channel data register 6 offeset.
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#define ADC_CDR7_OFF 0x0000004C ///< Channel data register 7 offeset.
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#define ADC_CDR0 (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF))) ///< Channel data register 0.
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#define ADC_CDR1 (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF))) ///< Channel data register 1.
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#define ADC_CDR2 (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF))) ///< Channel data register 2.
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#define ADC_CDR3 (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF))) ///< Channel data register 3.
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#define ADC_CDR4 (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF))) ///< Channel data register 4.
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#define ADC_CDR5 (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF))) ///< Channel data register 5.
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#define ADC_CDR6 (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF))) ///< Channel data register 6.
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#define ADC_CDR7 (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF))) ///< Channel data register 7.
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/* \} */
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#endif /* AT91_ADC_H */
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