191 lines
8.1 KiB
C
191 lines
8.1 KiB
C
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2008 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* AT91SAM7 Two wire interface.
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* This file is based on NUT/OS implementation. See license below.
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*/
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/*
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* Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (*((reg32_t *)(INCLUDING NEGLIGENCE OR OTHERWISE))) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* For additional information see http://www.ethernut.de/
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*/
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#ifndef AT91_TWI_H
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#define AT91_TWI_H
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/**
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* TWI Control Register.
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* \{
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*/
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#define TWI_CR_OFF 0x00000000 ///< Control register offset.
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#define TWI_CR (*((reg32_t *)(TWI_BASE + TWI_CR_OFF))) ///< Control register address.
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#define TWI_START 0 ///< Send start condition.
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#define TWI_STOP 1 ///< Send stop condition.
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#define TWI_MSEN 2 ///< Enable master mode.
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#define TWI_MSDIS 3 ///< Disable master mode.
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/*
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#define TWI_SVEN 4 ///< Enable slave mode.
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#define TWI_SVDIS 5 ///< Disable slave mode.
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*/
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#define TWI_SWRST 7 ///< Software reset.
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/*\}*/
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/**
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* TWI Master Mode Register.
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* \{
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*/
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#define TWI_MMR_OFF 0x00000004 ///< Master mode register offset.
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#define TWI_MMR (*((reg32_t *)(TWI_BASE + TWI_MMR_OFF))) ///< Master mode register address.
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#define TWI_IADRSZ_SHIFT 8 ///< Internal device address size shift.
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#define TWI_IADRSZ 0x00000300 ///< Internal device address size mask.
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#define TWI_IADRSZ_NONE 0x00000000 ///< No internal device address.
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#define TWI_IADRSZ_1BYTE 0x00000100 ///< One byte internal device address.
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#define TWI_IADRSZ_2BYTE 0x00000200 ///< Two byte internal device address.
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#define TWI_IADRSZ_3BYTE 0x00000300 ///< Three byte internal device address.
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#define TWI_MREAD 12 ///< Master read direction.
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#define TWI_DADR 0x007F0000 ///< Device address mask.
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#define TWI_DADR_SHIFT 16 ///< Device address LSB.
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/*\}*/
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/**
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* TWI Internal Address Register.
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* \{
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*/
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#define TWI_IADR_OFF 0x0000000C ///< Internal address register offset.
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#define TWI_IADR (*((reg32_t *)(TWI_BASE + TWI_IADR_OFF))) ///< Internal address register address.
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#define TWI_IADR_MASK 0x00FFFFFF ///< Internal address mask.
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#define TWI_IADR_SHIFT 0 ///< Internal address LSB.
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/*\}*/
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/**
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* TWI Clock Waveform Generator Register.
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* \{
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*/
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#define TWI_CWGR_OFF 0x00000010 ///< Clock waveform generator register offset.
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#define TWI_CWGR (*((reg32_t *)(TWI_BASE + TWI_CWGR_OFF))) ///< Clock waveform generator register address.
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#define TWI_CLDIV 0x000000FF ///< Clock low divider mask.
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#define TWI_CLDIV_SHIFT 0 ///< Clock low divider LSB.
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#define TWI_CHDIV 0x0000FF00 ///< Clock high divider mask.
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#define TWI_CHDIV_SHIFT 8 ///< Clock high divider LSB.
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#define TWI_CKDIV 0x00070000 ///< Clock divider mask.
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#define TWI_CKDIV_SHIFT 16 ///< Clock divider LSB.
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/*\}*/
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/**
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* TWI Status and Interrupt Registers.
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* \{
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*/
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#define TWI_SR_OFF 0x00000020 ///< Status register offset.
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#define TWI_SR (*((reg32_t *)(TWI_BASE + TWI_SR_OFF))) ///< Status register address.
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#define TWI_IER_OFF 0x00000024 ///< Interrupt enable register offset.
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#define TWI_IER (*((reg32_t *)(TWI_BASE + TWI_IER_OFF))) ///< Interrupt enable register address.
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#define TWI_IDR_OFF 0x00000028 ///< Interrupt disable register offset.
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#define TWI_IDR (*((reg32_t *)(TWI_BASE + TWI_IDR_OFF))) ///< Interrupt disable register address.
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#define TWI_IMR_OFF 0x0000002C ///< Interrupt mask register offset.
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#define TWI_IMR (*((reg32_t *)(TWI_BASE + TWI_IMR_OFF))) ///< Interrupt mask register address.
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#define TWI_TXCOMP 0 ///< Transmission completed.
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#define TWI_RXRDY 1 ///< Receive holding register ready.
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#define TWI_TXRDY 2 ///< Transmit holding register ready.
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/*
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#define TWI_SVREAD 0x00000008 ///< Slave read.
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#define TWI_SVACC 0x00000010 ///< Slave access.
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#define TWI_GACC 0x00000020 ///< General call access.
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*/
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#if CPU_ARM_SAM7X
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#define TWI_OVRE 6 ///< Overrun error.
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#define TWI_UNRE 7 ///< Underrun error.
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#endif
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#define TWI_NACK 8 ///< Not acknowledged.
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/*
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#define TWI_ARBLST 0x00000200 ///< Arbitration lost.
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#define TWI_SCLWS 0x00000400 ///< Clock wait state.
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#define TWI_EOSACC 0x00000800 ///< End of slave access.
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*/
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/*\}*/
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/**
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* TWI Receive Holding Register.
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* \{
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*/
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#define TWI_RHR_OFF 0x00000030 ///< Receive holding register offset.
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#define TWI_RHR (*((reg32_t *)(TWI_BASE + TWI_RHR_OFF))) ///< Receive holding register address.
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/*\}*/
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/**
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* TWI Transmit Holding Register.
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* \{
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*/
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#define TWI_THR_OFF 0x00000034 ///< Transmit holding register offset.
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#define TWI_THR (*((reg32_t *)(TWI_BASE + TWI_THR_OFF))) ///< Transmit holding register address.
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/*\}*/
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#endif /* AT91_TWI_H */
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