434 lines
14 KiB
C
434 lines
14 KiB
C
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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* \author Daniele Basile <asterix@develer.com>
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*
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* AT91SAM7 register definitions.
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* This file is based on NUT/OS implementation. See license below.
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*/
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/*
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* Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* For additional information see http://www.ethernut.de/
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*/
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#ifndef AT91SAM7_H
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#define AT91SAM7_H
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#include <cfg/compiler.h>
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#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
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#define FLASH_BASE 0x100000UL
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#define RAM_BASE 0x200000UL
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#define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
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#define UDP_BASE 0xFFFB0000 ///< USB device port base address.
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#define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
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#define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
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#define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
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#define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
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#define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
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#define ADC_BASE 0xFFFD8000 ///< ADC base address.
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#define AIC_BASE 0xFFFFF000 ///< AIC base address.
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#define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
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#define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
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#define PMC_BASE 0xFFFFFC00 ///< PMC base address.
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#define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
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#define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
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#define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
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#define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
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#define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
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#define MC_BASE 0xFFFFFF00 ///< Memory controller base.
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#if CPU_ARM_SAM7X
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#define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
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#define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
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#define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
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#define SPI1_BASE 0xFFFE4000 ///< SPI1 base address.
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#define PIOB_BASE 0xFFFFF600 ///< PIO base address.
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#endif
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#if CPU_ARM_SAM7S_LARGE
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#define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
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#endif
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#define PIO_HAS_MULTIDRIVER 1
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#define PIO_HAS_PULLUP 1
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#define PIO_HAS_PERIPHERALSELECT 1
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#define PIO_HAS_OUTPUTWRITEENABLE 1
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#define DBGU_HAS_PDC 1
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#define SPI_HAS_PDC 1
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#define SSC_HAS_PDC 1
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#define USART_HAS_PDC 1
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/* PDC registers */
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#define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register.
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#define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register.
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#define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register.
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#define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register.
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#define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
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#define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register.
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#define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
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#define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
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#define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register.
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#define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register.
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#define PDC_RXTEN 0
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#define PDC_RXTDIS 1
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#define PDC_TXTEN 8
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#define PDC_TXTDIS 9
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#else
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#error No base address register definition for selected ARM CPU
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#endif
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#if CPU_ARM_AT91SAM7S64
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#define FLASH_MEM_SIZE 0x10000UL ///< Internal flash memory size
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#define FLASH_PAGE_SIZE_BYTES 128 ///< Size of cpu flash memory page in bytes
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#define FLASH_BANKS_NUM 1 ///< Number of flash banks
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#define FLASH_SECTORS_NUM 16 ///< Number of flash sector
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#define FLASH_PAGE_PER_SECTOR 32 ///< Number of page for sector
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#elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128
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#define FLASH_MEM_SIZE 0x20000UL ///< Internal flash memory size
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#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
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#define FLASH_BANKS_NUM 1 ///< Number of flash banks
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#define FLASH_SECTORS_NUM 8 ///< Number of flash sector
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#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
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#elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
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#define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size
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#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
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#define FLASH_BANKS_NUM 1 ///< Number of flash banks
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#define FLASH_SECTORS_NUM 16 ///< Number of flash sector
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#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
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#elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512
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#define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size
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#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
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#define FLASH_BANKS_NUM 2 ///< Number of flash banks
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#define FLASH_SECTORS_NUM 32 ///< Number of flash sector
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#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
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#else
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#error Memory size definition for selected ARM CPU
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#endif
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#include "at91_aic.h"
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#include "at91_pit.h"
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#include "at91_pmc.h"
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#include "at91_mc.h"
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#include "at91_wdt.h"
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#include "at91_rstc.h"
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#include "at91_pio.h"
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#include "at91_us.h"
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#include "at91_dbgu.h"
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#include "at91_tc.h"
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#include "at91_adc.h"
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#include "at91_pwm.h"
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#include "at91_spi.h"
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#include "at91_twi.h"
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#include "at91_ssc.h"
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#include "at91_emac.h"
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//TODO: add other peripherals
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/**
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* Peripheral Identifiers and Interrupts
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*\{
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*/
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#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
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#define FIQ_ID 0 ///< Fast interrupt ID.
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#define SYSC_ID 1 ///< System controller interrupt.
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#define US0_ID 6 ///< USART 0 ID.
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#define US1_ID 7 ///< USART 1 ID.
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#define SSC_ID 8 ///< Synchronous serial controller ID.
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#define TWI_ID 9 ///< Two-wire interface ID.
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#define PWMC_ID 10 ///< PWM controller ID.
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#define UDP_ID 11 ///< USB device port ID.
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#define TC0_ID 12 ///< Timer 0 ID.
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#define TC1_ID 13 ///< Timer 1 ID.
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#define TC2_ID 14 ///< Timer 2 ID.
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#define IRQ0_ID 30 ///< External interrupt 0 ID.
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#define IRQ1_ID 31 ///< External interrupt 1 ID.
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#if CPU_ARM_SAM7X
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#define PIOA_ID 2 ///< Parallel A I/O controller ID.
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#define PIOB_ID 3 ///< Parallel B I/O controller ID.
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#define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
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#define SPI1_ID 5 ///< Serial peripheral interface 1 ID.
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#define CAN_ID 15 ///< CAN controller ID.
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#define EMAC_ID 16 ///< Ethernet MAC ID.
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#define ADC_ID 17 ///< Analog to digital converter ID.
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/* 18-29 Reserved */
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#endif
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#if CPU_ARM_SAM7S_LARGE
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#define PIOA_ID 2 ///< Parallel I/O controller ID.
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/* ID 3 is reserved */
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#define ADC_ID 4 ///< Analog to digital converter ID.
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#define SPI_ID 5 ///< Serial peripheral interface ID.
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#define SPI0_ID SPI_ID ///< Alias
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#endif
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#else
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#error No peripheral ID and interrupts definition for selected ARM CPU
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#endif
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/*\}*/
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/**
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* USART & DEBUG pin names
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*\{
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*/
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#if CPU_ARM_SAM7S_LARGE
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#define RXD0 5
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#define TXD0 6
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#define RXD1 21
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#define TXD1 22
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#define DTXD 10
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#define DRXD 9
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#elif CPU_ARM_SAM7X
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#define RXD0 0 // PA0
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#define TXD0 1 // PA1
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#define RXD1 5 // PA5
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#define TXD1 6 // PA6
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#define DTXD 28 // PA28
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#define DRXD 27 // PA27
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#else
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#error No USART & debug pin names definition for selected ARM CPU
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#endif
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/*\}*/
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/**
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* SPI pins name
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*\{
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*/
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#if CPU_ARM_SAM7S_LARGE
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#define SPI0_NPCS0 11 // Same as NSS pin.
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#define SPI0_MISO 12
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#define SPI0_MOSI 13
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#define SPI0_SPCK 14
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#elif CPU_ARM_SAM7X
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#define SPI0_NPCS0 12 // Same as NSS pin. PA12
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#define SPI0_NPCS1 13 // PA13
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#define SPI0_NPCS2 14 // PA14
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#define SPI0_NPCS3 15 // PA15
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#define SPI0_MISO 16 // PA16
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#define SPI0_MOSI 17 // PA17
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#define SPI0_SPCK 18 // PA18
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#define SPI1_NPCS0 21 // Same as NSS pin. PA21
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#define SPI1_NPCS1 25 // PA25
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#define SPI1_NPCS2 26 // PA26
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#define SPI1_NPCS3 29 // PA29
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#define SPI1_MISO 24 // PA24
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#define SPI1_MOSI 23 // PA23
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#define SPI1_SPCK 22 // PA22
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#else
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#error No SPI pins name definition for selected ARM CPU
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#endif
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/*\}*/
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/**
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* SSC pins name
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*\{
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*/
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#if CPU_ARM_SAM7S_LARGE
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#define SSC_TF 15 // PA15
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#define SSC_TK 16 // PA16
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#define SSC_TD 17 // PA17
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#define SSC_RD 18 // PA18
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#define SSC_RK 19 // PA19
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#define SSC_RF 20 // PA20
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#elif CPU_ARM_SAM7X
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#define SSC_TF 21 // PA21
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#define SSC_TK 22 // PA22
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#define SSC_TD 23 // PA23
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#define SSC_RD 24 // PA24
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#define SSC_RK 25 // PA25
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#define SSC_RF 26 // PA26
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#else
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#error No SSC pins name definition for selected ARM CPU
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#endif
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/*\}*/
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/**
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* Timer counter pins definition.
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*\{
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*/
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#if CPU_ARM_SAM7X
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#define TIOA0 23 // PB23
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#define TIOB0 24 // PB24
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#define TIOA1 25 // PB25
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#define TIOB1 26 // PB26
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#define TIOA2 27 // PB27
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#define TIOB2 28 // PB28
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#define TIO_PIO_PDR PIOB_PDR
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#define TIO_PIO_ABSR PIOB_ASR
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#elif CPU_ARM_SAM7S_LARGE
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#define TIOA0 0 // PA0
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#define TIOB0 1 // PA1
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#define TIOA1 15 // PA15
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#define TIOB1 16 // PA16
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#define TIOA2 26 // PA26
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#define TIOB2 27 // PA27
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#define TIO_PIO_PDR PIOA_PDR
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||
|
|
#define TIO_PIO_ABSR PIOA_BSR
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||
|
|
|
||
|
|
#else
|
||
|
|
#error No Timer Counter names of pins definition for selected ARM CPU
|
||
|
|
|
||
|
|
#endif
|
||
|
|
/*\}*/
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* PWM pins definition.
|
||
|
|
*\{
|
||
|
|
*/
|
||
|
|
#if CPU_ARM_SAM7X
|
||
|
|
#define PWM0 19 // PB19
|
||
|
|
#define PWM1 20 // PB20
|
||
|
|
#define PWM2 21 // PB21
|
||
|
|
#define PWM3 22 // PB22
|
||
|
|
|
||
|
|
#define PWM_PIO_PDR PIOB_PDR
|
||
|
|
#define PWM_PIO_PER PIOB_PER
|
||
|
|
#define PWM_PIO_CODR PIOB_CODR
|
||
|
|
#define PWM_PIO_OER PIOB_OER
|
||
|
|
#define PWM_PIO_ABSR PIOB_ASR
|
||
|
|
|
||
|
|
#elif CPU_ARM_SAM7S_LARGE
|
||
|
|
#define PWM0 11 // PA11
|
||
|
|
#define PWM1 12 // PA12
|
||
|
|
#define PWM2 13 // PA13
|
||
|
|
#define PWM3 14 // PA14
|
||
|
|
|
||
|
|
#define PWM_PIO_PDR PIOA_PDR
|
||
|
|
#define PWM_PIO_PER PIOA_PER
|
||
|
|
#define PWM_PIO_CODR PIOA_CODR
|
||
|
|
#define PWM_PIO_OER PIOA_OER
|
||
|
|
#define PWM_PIO_ABSR PIOA_BSR
|
||
|
|
|
||
|
|
#else
|
||
|
|
#error No PWM names of pins definition for selected ARM CPU
|
||
|
|
|
||
|
|
#endif
|
||
|
|
/*\}*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* TWI pins definition.
|
||
|
|
*\{
|
||
|
|
*/
|
||
|
|
#if CPU_ARM_SAM7X
|
||
|
|
#define TWD 10
|
||
|
|
#define TWCK 11
|
||
|
|
|
||
|
|
#elif CPU_ARM_SAM7S_LARGE
|
||
|
|
#define TWD 3 //PA3
|
||
|
|
#define TWCK 4 //PA4
|
||
|
|
|
||
|
|
#else
|
||
|
|
#error No TWI names of pins definition for selected ARM CPU
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/**
|
||
|
|
* ADC pins definition.
|
||
|
|
*\{
|
||
|
|
*/
|
||
|
|
#if CPU_ARM_SAM7X
|
||
|
|
#define ADTRG 18 // PB18
|
||
|
|
#define AD0 23 // PB27
|
||
|
|
#define AD1 24 // PB28
|
||
|
|
#define AD2 25 // PB29
|
||
|
|
#define AD3 26 // PB30
|
||
|
|
|
||
|
|
#elif CPU_ARM_SAM7S_LARGE
|
||
|
|
#define ADTRG 18 // PA8
|
||
|
|
#define AD0 0 // PA17
|
||
|
|
#define AD1 1 // PA18
|
||
|
|
#define AD2 15 // PA19
|
||
|
|
#define AD3 16 // PA20
|
||
|
|
|
||
|
|
#else
|
||
|
|
#error No ADC names of pins definition for selected ARM CPU
|
||
|
|
|
||
|
|
#endif
|
||
|
|
/*\}*/
|
||
|
|
|
||
|
|
#endif /* AT91SAM7_H */
|