/** * \file * * * \brief Macro for HW_SIPO_H * * * * \author Andrea Grandi * \author Daniele Basile */ #ifndef HW_SIPO_H #define HW_SIPO_H /** * Map sipo connection on board. */ typedef enum SipoMap { SIPO_CNT } SipoMap; /** * Define generic macro to set pins logic level */ #define SIPO_SET_LEVEL_LOW(dev) do { /* Implement me! */ } while (0) #define SIPO_SET_LEVEL_HIGH(dev) do { /* Implement me! */ } while (0) /** * Generate one low pulse on select line. */ #define PULSE_LOW(dev) do { /* Implement me! */ } while (0) /** * Generate one hight pulse on select line. */ #define PULSE_HIGH(dev) do { /* Implement me! */ } while (0) /** * Define the procedure to drive serial input in sipo device (SI). */ #define SIPO_SI_HIGH() do { /* Implement me! */ } while (0) #define SIPO_SI_LOW() do { /* Implement me! */ } while (0) /** * Drive clock to shift SI data into latch. */ #define SIPO_SI_CLOCK(clk_pol) \ do { \ (void)clk_pol; \ /* Implement me! */ \ } while (0) /** * Do everything needed in order to load dato into sipo. */ #define SIPO_LOAD(device, load_pol) do { /* Implement me! */ } while (0) /** * Enable the shift register output. */ #define SIPO_ENABLE() do { /* Implement me! */ } while (0) /** * Set polarity for Load, Clk, SI signals. */ #define SIPO_SET_LD_LEVEL(device, load_pol) do { /* Implement me! */ } while (0) #define SIPO_SET_CLK_LEVEL(clock_pol) do { /* Implement me! */ } while (0) #define SIPO_SET_SI_LEVEL() do { /* Implement me! */ } while (0) /** * Do anything that needed to init sipo pins. */ #define SIPO_INIT_PIN() do { /* Implement me! */ } while (0) #endif /* HW_SIPO_H */