737 lines
22 KiB
C
737 lines
22 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
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* Copyright 2011 Onno <developer@gorgoz.org>
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*
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* -->
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*
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* \brief AVR XMEGA USART driver (Implementation)
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*
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* This file is heavily inspired by the AVR implementation for BeRTOS,
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* but uses a different approach for implementing the different debug
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* ports, by using the USART_t structs.
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*
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* \author Onno <developer@gorgoz.org>
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* notest:all
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*/
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#include "hw/hw_ser.h" /* Required for bus macros overrides */
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#include <hw/hw_cpufreq.h> /* CPU_FREQ */
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#include "cfg/cfg_ser.h" /* Serialport configuration settings */
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#include <cfg/macros.h> /* DIV_ROUND */
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#include <cfg/debug.h> /* debug configuration */
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#include <drv/ser.h>
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#include <drv/ser_p.h>
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#include <drv/timer.h>
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#include <struct/fifobuf.h>
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#include <avr/io.h> /* AVR IO ports and structures */
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#include <avr/interrupt.h> /* AVR Interrupt methods */
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/*
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* Scalefactor to use for computing the baudrate
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* this scalefactor should be an integer value between -7
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* and 7
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*/
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#ifndef USART_SCALE_FACTOR
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#define USART_SCALE_FACTOR (-7)
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#else
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#if USART_SCALE_FACTOR > 7 || USART_SCALE_FACTOR < -7
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#error USART_SCALE_FACTOR should be an integer between -7 and 7
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#endif
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#endif
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/* Helper macros, mostly taken from the Atmel Examples
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* Slightly alterd to match the BeRTOS naming convention
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*/
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/* \brief Set USART baud rate.
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*
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* Sets the USART's baud rate register.
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*
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* UBRR_Value : Value written to UBRR
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* ScaleFactor : Time Base Generator Scale Factor
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*
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* Equation for calculation of BSEL value in asynchronous normal speed mode:
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* If ScaleFactor >= 0
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* BSEL = ((I/O clock frequency)/(2^(ScaleFactor)*16*Baudrate))-1
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* If ScaleFactor < 0
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* BSEL = (1/(2^(ScaleFactor)*16))*(((I/O clock frequency)/Baudrate)-1)
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*
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* \note See XMEGA manual for equations for calculation of BSEL value in other
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* modes.
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*
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* \param _usart Pointer to the USART module.
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* \param _bselValue Value to write to BSEL part of Baud control register.
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* Use uint16_t type.
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* \param _bScaleFactor USART baud rate scale factor.
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* Use uint8_t type
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*/
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#define USART_SET_BAUDRATE(_usart, _bselValue, _bScaleFactor) \
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(_usart)->BAUDCTRLA =(uint8_t)_bselValue; \
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(_usart)->BAUDCTRLB =(_bScaleFactor << USART_BSCALE0_bp)|(_bselValue >> 8)
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/* \brief Enable USART receiver.
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*
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* \param _usart Pointer to the USART module
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*/
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#define USART_RX_ENABLE(_usart) ((_usart)->CTRLB |= USART_RXEN_bm)
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/* \brief Disable USART receiver.
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*
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* \param _usart Pointer to the USART module.
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*/
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#define USART_RX_DISABLE(_usart) ((_usart)->CTRLB &= ~USART_RXEN_bm)
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/* \brief Enable USART transmitter.
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*
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* \param _usart Pointer to the USART module.
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*/
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#define USART_TX_ENABLE(_usart) ((_usart)->CTRLB |= USART_TXEN_bm)
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/* \brief Disable USART transmitter.
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*
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* \param _usart Pointer to the USART module.
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*/
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#define USART_TX_DISABLE(_usart) ((_usart)->CTRLB &= ~USART_TXEN_bm)
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/* \brief Set USART RXD interrupt level.
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*
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* Sets the interrupt level on RX Complete interrupt.
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*
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* \param _usart Pointer to the USART module.
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* \param _rxdIntLevel Interrupt level of the RXD interrupt.
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* Use USART_RXCINTLVL_t type.
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*/
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#define USART_SET_RX_INTERRUPT_LEVEL(_usart, _rxdIntLevel) \
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((_usart)->CTRLA = ((_usart)->CTRLA & ~USART_RXCINTLVL_gm) | _rxdIntLevel)
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/* \brief Set USART TXD interrupt level.
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*
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* Sets the interrupt level on TX Complete interrupt.
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*
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* \param _usart Pointer to the USART module.
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* \param _txdIntLevel Interrupt level of the TXD interrupt.
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* Use USART_TXCINTLVL_t type.
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*/
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#define USART_SET_TX_INTERRUPT_LEVEL(_usart, _txdIntLevel) \
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(_usart)->CTRLA = ((_usart)->CTRLA & ~USART_TXCINTLVL_gm) | _txdIntLevel
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/* \brief Set USART DRE interrupt level.
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*
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* Sets the interrupt level on Data Register interrupt.
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*
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* \param _usart Pointer to the USART module.
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* \param _dreIntLevel Interrupt level of the DRE interrupt.
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* Use USART_DREINTLVL_t type.
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*/
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#define USART_SET_DRE_INTERRUPT_LEVEL(_usart, _dreIntLevel) \
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(_usart)->CTRLA = ((_usart)->CTRLA & ~USART_DREINTLVL_gm) | _dreIntLevel
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/* \brief Set the mode the USART run in.
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*
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* Set the mode the USART run in. The default mode is asynchronous mode.
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*
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* \param _usart Pointer to the USART module register section.
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* \param _usartMode Selects the USART mode. Use USART_CMODE_t type.
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*
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* USART modes:
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* - 0x0 : Asynchronous mode.
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* - 0x1 : Synchronous mode.
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* - 0x2 : IrDA mode.
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* - 0x3 : Master SPI mode.
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*/
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#define USART_SET_MODE(_usart, _usartMode) \
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((_usart)->CTRLC = ((_usart)->CTRLC & (~USART_CMODE_gm)) | _usartMode)
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/* \brief Check if data register empty flag is set.
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*
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* \param _usart The USART module.
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*/
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#define USART_IS_TX_DATA_REGISTER_EMPTY(_usart) (((_usart)->STATUS & USART_DREIF_bm) != 0)
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/* \brief Put data (5-8 bit character).
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*
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* Use the macro USART_IsTXDataRegisterEmpty before using this function to
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* put data to the TX register.
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*
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* \param _usart The USART module.
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* \param _data The data to send.
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*/
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#define USART_PUT_CHAR(_usart, _data) ((_usart)->DATA = _data)
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/* \brief Checks if the RX complete interrupt flag is set.
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*
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* Checks if the RX complete interrupt flag is set.
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*
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* \param _usart The USART module.
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*/
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#define USART_IS_RX_COMPLETE(_usart) (((_usart)->STATUS & USART_RXCIF_bm) != 0)
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/* \brief Get received data (5-8 bit character).
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*
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* This macro reads out the RX register.
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* Use the macro USART_RX_Complete to check if anything is received.
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*
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* \param _usart The USART module.
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*
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* \retval Received data.
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*/
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#define USART_GET_CHAR(_usart) ((_usart)->DATA)
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/* configurable macros */
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#if !CONFIG_SER_HWHANDSHAKE
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/**
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* \name Hardware handshake (RTS/CTS).
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* \{
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*/
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#define RTS_ON do {} while (0)
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#define RTS_OFF do {} while (0)
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#define IS_CTS_ON true
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#define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
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/*\}*/
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#endif
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/*
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* \name Overridable serial bus hooks
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*
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* These can be redefined in hw.h to implement
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* special bus policies such as half-duplex, 485, etc.
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*
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*
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* \code
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* TXBEGIN TXCHAR TXEND TXOFF
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* | __________|__________ | |
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* | | | | | | | | |
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* v v v v v v v v v
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* ______ __ __ __ __ __ __ ________________
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* \/ \/ \/ \/ \/ \/ \/
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* ______/\__/\__/\__/\__/\__/\__/
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*
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* \endcode
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*
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* \{
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*/
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#ifndef SER_UART_BUS_TXINIT
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/*
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* Default TXINIT macro - invoked in uart_init()
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*
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* - Enable both the receiver and the transmitter
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* - Enable only the RX complete interrupt
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*/
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#define SER_UART_BUS_TXINIT(_usart) do { \
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USART_RX_ENABLE(_usart); \
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USART_TX_ENABLE(_usart); \
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USART_SET_RX_INTERRUPT_LEVEL(_usart, USART_RXCINTLVL_MED_gc); \
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} while (0)
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#endif
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#ifndef SER_UART_BUS_TXBEGIN
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/*
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* Invoked before starting a transmission
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*
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* - Enable both the receiver and the transmitter
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* - Enable both the RX complete and UDR empty interrupts
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*/
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#define SER_UART_BUS_TXBEGIN(_usart) do { \
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USART_SET_RX_INTERRUPT_LEVEL(_usart, USART_RXCINTLVL_MED_gc); \
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USART_SET_DRE_INTERRUPT_LEVEL(_usart, USART_DREINTLVL_MED_gc);\
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} while (0)
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#endif
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#ifndef SER_UART_BUS_TXCHAR
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/*
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* Invoked to send one character.
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*/
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#define SER_UART_BUS_TXCHAR(_usart, c) do { \
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USART_PUT_CHAR(_usart, c); \
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} while (0)
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#endif
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#ifndef SER_UART_BUS_TXEND
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/*
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* Invoked as soon as the txfifo becomes empty
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*
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* - Keep both the receiver and the transmitter enabled
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* - Keep the RX complete interrupt enabled
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* - Disable the UDR empty interrupt
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*/
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#define SER_UART_BUS_TXEND(_usart) do { \
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USART_SET_DRE_INTERRUPT_LEVEL(_usart, USART_DREINTLVL_OFF_gc); \
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} while (0)
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#endif
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#ifndef SER_UART_BUS_TXOFF
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/*
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* \def SER_UART_BUS_TXOFF
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*
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* Invoked after the last character has been transmitted
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*
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* The default is no action.
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*/
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#ifdef __doxygen__
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#define SER_UART_BUS_TXOFF(_usart)
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#endif
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#endif
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/*\}*/
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/* From the high-level serial driver */
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extern struct Serial *ser_handles[SER_CNT];
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/* TX and RX buffers */
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static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
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static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
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static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
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static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
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#ifdef CPU_AVR_XMEGA_A
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static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
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static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
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static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
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static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
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static unsigned char uart4_txbuffer[CONFIG_UART4_TXBUFSIZE];
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static unsigned char uart4_rxbuffer[CONFIG_UART4_RXBUFSIZE];
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#endif
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/*
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* Internal hardware state structure
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*
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* The \a sending variable is true while the transmission
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* interrupt is retriggering itself.
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*
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* the \a usart variable will point to the USART_t structure
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* that should be used.
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*
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* the \a port variable will point to the PORT_t structure
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* that should be modified to set the tx pin as an output and the
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* rx pin as an input
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*
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* the \a txpin variable will hold the pinnumber of the pin to use
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* as the tx output
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*
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* the \a rxpin variable will hold the pinnumber of the pin to use
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* as the rx input
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*
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* For the USARTs the \a sending flag is useful for taking specific
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* actions before sending a burst of data, at the start of a trasmission
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* but not before every char sent.
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*
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* For the SPI, this flag is necessary because the SPI sends and receives
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* bytes at the same time and the SPI IRQ is unique for send/receive.
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* The only way to start transmission is to write data in SPDR (this
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* is done by spi_starttx()). We do this *only* if a transfer is
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* not already started.
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*/
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struct AvrxmegaSerial
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{
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struct SerialHardware hw;
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volatile bool sending;
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volatile USART_t* usart;
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volatile PORT_t* port;
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uint8_t txpin;
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uint8_t rxpin;
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};
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/*
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* Callbacks
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* The same callbacks are used for all USARTS.
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* By casting the SerialHardware structure to the AvrxmegaSerial
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* structure a pointer to the USART_t structure can be obtained,
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* to perform the callback for the specific USART.
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* This methode might cost some more cpu time, but saves on
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* code duplication and code size.
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*/
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/*
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* \brief Initializes the uart
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*
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* The TX pin of the uart will be set as an outputpin
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* The RX pin of the uart will be set as an inputpin
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* The usart will be initialized
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* \see SER_UART_BUS_TXINIT
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*
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* \param _hw struct AvrxmegaSerial
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* \param ser Unused
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*/
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static void uart_init(struct SerialHardware * _hw, UNUSED_ARG(struct Serial *, ser))
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{
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struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
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//set transmit pin as output
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hw->port->DIRSET = BV(hw->txpin);
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hw->port->OUTCLR = BV(hw->txpin);
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//set receive pin as input
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hw->port->DIRCLR = BV(hw->rxpin);
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//initialize the USART
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SER_UART_BUS_TXINIT(hw->usart);
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RTS_ON;
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SER_STROBE_INIT;
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}
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/*
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* \brief Cleans up / Disables the uart
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*
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* \param _hw struct AvrxmegaSerial
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*/
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static void uart_cleanup(struct SerialHardware * _hw)
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{
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struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
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hw->usart->CTRLA = 0;
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hw->usart->CTRLB = 0;
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}
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/*
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* \brief Enableds the TX interrupt
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*
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* \param _hw struct AvrxmegaSerial
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*/
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static void uart_enabletxirq(struct SerialHardware *_hw)
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{
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struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
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/*
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* WARNING: racy code here! The tx interrupt sets hw->sending to false
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* when it runs with an empty fifo. The order of statements in the
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* if-block matters.
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*/
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if (!hw->sending)
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{
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hw->sending = true;
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SER_UART_BUS_TXBEGIN(hw->usart);
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}
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}
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/*
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* \brief sets the uart to the provided baudrate
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*
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* For setting the baudrate an scale factor (bscale) and a period
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* setting (BSEL) is required.
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*
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* The scale factor should be privided by defining USART_SCALE_FACTOR
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*
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* Atmel specifies BSEL for normal speed mode and bscale >= 0 as:
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* BSEL = (cpu_freq / ((2^bscale) * 16 * rate)) - 1
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* To allow BSEL to be calculated with an power function this can be
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* rewriten to:
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* BSEL = BSEL = (cpu_freq / ((1 << bscale) * 16 * rate)) - 1
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*
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* Atmel specifies BSEL for normal speed mode and bscale < 0 as:
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* BSEL = (1 / (2^bscale)) * ( (cpu_freq / (16 * rate)) - 1)
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* To calculte this float atheritmic is required as the second product will be smaller
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* than zero in a lot of cases.
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* To allow BSEL to be calculated with interger devision and no power function
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* this can be rewriten by folowing simple math rules to:
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* BSEL = ((1 << -bscale) * (cpu_freq - (16 * rate)) / (16 * rate)
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*
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* \param _hw struct AvrxmegaSerial
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* \param _rate the required baudrate
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*
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*/
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static void uart_setbaudrate(struct SerialHardware * _hw, unsigned long _rate)
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{
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struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
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/* Compute baud-rate period, this requires a valid USART_SCALE_FACTOR */
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#if USART_SCALE_FACTOR < 0
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uint16_t bsel = DIV_ROUND((1 << (-(USART_SCALE_FACTOR))) * (CPU_FREQ - (16 * _rate)), 16 * _rate);
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#else
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uint16_t bsel = DIV_ROUND(CPU_FREQ, (1 << (USART_SCALE_FACTOR)) * 16 * _rate) - 1;
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#endif
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USART_SET_BAUDRATE(hw->usart, bsel, USART_SCALE_FACTOR);
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}
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/*
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* \brief Sets the parity of the uart
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*
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* \param _hw struct AvrxmegaSerial
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* \param _parity the parity to set
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*/
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static void uart_setparity(struct SerialHardware * _hw, int _parity)
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{
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struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
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USART_SET_MODE(hw->usart, _parity);
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}
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/*
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* \brief Returns true if Transmitter is sending
|
|
*
|
|
* \param _hw struct AvrxmegaSerial
|
|
* \return true if transmitter is sending
|
|
*/
|
|
static bool tx_sending(struct SerialHardware* _hw)
|
|
{
|
|
struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
|
|
return hw->sending;
|
|
}
|
|
|
|
|
|
// FIXME: move into compiler.h? Ditch?
|
|
#if COMPILER_C99
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|
#define C99INIT(name,val) .name = val
|
|
#elif defined(__GNUC__)
|
|
#define C99INIT(name,val) name: val
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|
#else
|
|
#warning No designated initializers, double check your code
|
|
#define C99INIT(name,val) (val)
|
|
#endif
|
|
|
|
/*
|
|
* High-level interface data structures
|
|
*/
|
|
static const struct SerialHardwareVT UART_VT =
|
|
{
|
|
C99INIT(init, uart_init),
|
|
C99INIT(cleanup, uart_cleanup),
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|
C99INIT(setBaudrate, uart_setbaudrate),
|
|
C99INIT(setParity, uart_setparity),
|
|
C99INIT(txStart, uart_enabletxirq),
|
|
C99INIT(txSending, tx_sending)
|
|
};
|
|
|
|
static struct AvrxmegaSerial UARTDescs[SER_CNT] =
|
|
{
|
|
{
|
|
C99INIT(hw, /**/) {
|
|
C99INIT(table, &UART_VT),
|
|
C99INIT(txbuffer, uart0_txbuffer),
|
|
C99INIT(rxbuffer, uart0_rxbuffer),
|
|
C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
|
|
C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
|
|
},
|
|
C99INIT(sending, false),
|
|
C99INIT(usart, &USARTC0),
|
|
C99INIT(port, &PORTC),
|
|
C99INIT(txpin, PIN3_bp),
|
|
C99INIT(rxpin, PIN2_bp),
|
|
},
|
|
{
|
|
C99INIT(hw, /**/) {
|
|
C99INIT(table, &UART_VT),
|
|
C99INIT(txbuffer, uart1_txbuffer),
|
|
C99INIT(rxbuffer, uart1_rxbuffer),
|
|
C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
|
|
C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
|
|
},
|
|
C99INIT(sending, false),
|
|
C99INIT(usart, &USARTD0),
|
|
C99INIT(port, &PORTD),
|
|
C99INIT(txpin, PIN3_bp),
|
|
C99INIT(rxpin, PIN2_bp),
|
|
},
|
|
#ifdef CPU_AVR_XMEGA_A
|
|
{
|
|
C99INIT(hw, /**/) {
|
|
C99INIT(table, &UART_VT),
|
|
C99INIT(txbuffer, uart2_txbuffer),
|
|
C99INIT(rxbuffer, uart2_rxbuffer),
|
|
C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
|
|
C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
|
|
},
|
|
C99INIT(sending, false),
|
|
C99INIT(usart, &USARTC1),
|
|
C99INIT(port, &PORTC),
|
|
C99INIT(txpin, PIN7_bp),
|
|
C99INIT(rxpin, PIN6_bp),
|
|
},
|
|
{
|
|
C99INIT(hw, /**/) {
|
|
C99INIT(table, &UART_VT),
|
|
C99INIT(txbuffer, uart3_txbuffer),
|
|
C99INIT(rxbuffer, uart3_rxbuffer),
|
|
C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
|
|
C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
|
|
},
|
|
C99INIT(sending, false),
|
|
C99INIT(usart, &USARTD1),
|
|
C99INIT(port, &PORTD),
|
|
C99INIT(txpin, PIN7_bp),
|
|
C99INIT(rxpin, PIN6_bp),
|
|
},
|
|
{
|
|
C99INIT(hw, /**/) {
|
|
C99INIT(table, &UART_VT),
|
|
C99INIT(txbuffer, uart4_txbuffer),
|
|
C99INIT(rxbuffer, uart4_rxbuffer),
|
|
C99INIT(txbuffer_size, sizeof(uart4_txbuffer)),
|
|
C99INIT(rxbuffer_size, sizeof(uart4_rxbuffer)),
|
|
},
|
|
C99INIT(sending, false),
|
|
C99INIT(usart, &USARTE0),
|
|
C99INIT(port, &PORTE),
|
|
C99INIT(txpin, PIN3_bp),
|
|
C99INIT(rxpin, PIN2_bp),
|
|
},
|
|
#endif //CPU_AVR_XMEGA_A
|
|
};
|
|
|
|
struct SerialHardware *ser_hw_getdesc(int unit)
|
|
{
|
|
ASSERT(unit < SER_CNT);
|
|
return &UARTDescs[unit].hw;
|
|
}
|
|
|
|
|
|
/*
|
|
* Interrupt handlers
|
|
*/
|
|
static inline void usart_handleDreInterrupt(uint8_t usartNumber)
|
|
{
|
|
SER_STROBE_ON;
|
|
struct FIFOBuffer * const txfifo = &ser_handles[usartNumber]->txfifo;
|
|
if (fifo_isempty(txfifo))
|
|
{
|
|
SER_UART_BUS_TXEND(UARTDescs[usartNumber].usart);
|
|
#ifndef SER_UART_BUS_TXOFF
|
|
UARTDescs[usartNumber].sending = false;
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
char c = fifo_pop(txfifo);
|
|
SER_UART_BUS_TXCHAR(UARTDescs[usartNumber].usart, c);
|
|
}
|
|
SER_STROBE_OFF;
|
|
}
|
|
|
|
#define USART_DRE_INTERRUPT_VECTOR(_vector, _usart) \
|
|
DECLARE_ISR(_vector) \
|
|
{ \
|
|
usart_handleDreInterrupt( _usart ); \
|
|
}
|
|
|
|
USART_DRE_INTERRUPT_VECTOR(USARTC0_DRE_vect, SER_UART0)
|
|
USART_DRE_INTERRUPT_VECTOR(USARTD0_DRE_vect, SER_UART1)
|
|
#ifdef CPU_AVR_XMEGA_A
|
|
USART_DRE_INTERRUPT_VECTOR(USARTC1_DRE_vect, SER_UART2)
|
|
USART_DRE_INTERRUPT_VECTOR(USARTD1_DRE_VECT, SER_UART3)
|
|
USART_DRE_INTERRUPT_VECTOR(USARTE0_DRE_vect, SER_UART4)
|
|
#endif
|
|
|
|
#ifdef SER_UART_BUS_TXOFF
|
|
static inline void USART_handleTXCInterrupt(uint8_t usartNumber)
|
|
{
|
|
SER_STROBE_ON;
|
|
struct FIFOBuffer * const txfifo = &ser_handles[usartNumber]->txfifo;
|
|
if (fifo_isempty(txfifo))
|
|
{
|
|
SER_UART_BUS_TXOFF(UARTDescs[usartNumber].usart);
|
|
UARTDescs[usartNumber].sending = false;
|
|
}
|
|
else
|
|
{
|
|
SER_UART_BUS_TXBEGIN(UARTDescs[usartNumber].usart);
|
|
}
|
|
SER_STROBE_OFF;
|
|
}
|
|
|
|
/*
|
|
* Serial port 0 TX complete interrupt handler.
|
|
*
|
|
* This IRQ is usually disabled. The UDR-empty interrupt
|
|
* enables it when there's no more data to transmit.
|
|
* We need to wait until the last character has been
|
|
* transmitted before switching the 485 transceiver to
|
|
* receive mode.
|
|
*
|
|
* The txfifo might have been refilled by putchar() while
|
|
* we were waiting for the transmission complete interrupt.
|
|
* In this case, we must restart the UDR empty interrupt,
|
|
* otherwise we'd stop the serial port with some data
|
|
* still pending in the buffer.
|
|
*/
|
|
#define USART_TXC_INTERRUPT_VECTOR(_vector, _usart) \
|
|
DECLARE_ISR(_vector) \
|
|
{ \
|
|
USART_handleTXCInterrupt( _usart ); \
|
|
}
|
|
|
|
USART_TXC_INTERRUPT_VECTOR(USARTC0_TXC_vect, SER_UART0)
|
|
USART_TXC_INTERRUPT_VECTOR(USARTD0_TXC_vect, SER_UART1)
|
|
#ifdef CPU_AVR_XMEGA_A
|
|
USART_TXC_INTERRUPT_VECTOR(USARTC1_TXC_vect, SER_UART2)
|
|
USART_TXC_INTERRUPT_VECTOR(USARTD1_TXC_vect, SER_UART3)
|
|
USART_TXC_INTERRUPT_VECTOR(USARTE0_TXC_vect, SER_UART4)
|
|
#endif /* CPU_AVR_XMEGA_A */
|
|
#endif /* SER_UART_BUS_TXOFF */
|
|
|
|
/*
|
|
* Serial RX complete interrupt handler.
|
|
*
|
|
* This handler is interruptible.
|
|
* Interrupt are reenabled as soon as recv complete interrupt is
|
|
* disabled. Using INTERRUPT() is troublesome when the serial
|
|
* is heavily loaded, because an interrupt could be retriggered
|
|
* when executing the handler prologue before RXCIE is disabled.
|
|
*/
|
|
static inline void USART_handleRXCInterrupt(uint8_t usartNumber)
|
|
{
|
|
SER_STROBE_ON;
|
|
/* read status */
|
|
ser_handles[usartNumber]->status |= (UARTDescs[usartNumber].usart)->STATUS & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
|
|
/* To clear the RXC flag we must _always_ read the UDR even when we're
|
|
* not going to accept the incoming data, otherwise a new interrupt
|
|
* will occur once the handler terminates.
|
|
*/
|
|
char c = (UARTDescs[usartNumber].usart)->DATA;
|
|
struct FIFOBuffer * const rxfifo = &ser_handles[usartNumber]->rxfifo;
|
|
if (fifo_isfull(rxfifo))
|
|
{
|
|
ser_handles[usartNumber]->status |= SERRF_RXFIFOOVERRUN;
|
|
}
|
|
else
|
|
{
|
|
fifo_push(rxfifo, c);
|
|
#if CONFIG_SER_HWHANDSHAKE
|
|
if (fifo_isfull(rxfifo))
|
|
{
|
|
RTS_OFF(UARTDescs[usartNumber].usart);
|
|
}
|
|
#endif
|
|
}
|
|
SER_STROBE_OFF;
|
|
}
|
|
|
|
#define USART_RXC_INTERRUPT_VECTOR(_vector, _usart) \
|
|
DECLARE_ISR(_vector) \
|
|
{ \
|
|
USART_handleRXCInterrupt( _usart ); \
|
|
}
|
|
USART_RXC_INTERRUPT_VECTOR(USARTC0_RXC_vect, SER_UART0)
|
|
USART_RXC_INTERRUPT_VECTOR(USARTD0_RXC_vect, SER_UART1)
|
|
#ifdef CPU_AVR_XMEGA_A
|
|
USART_RXC_INTERRUPT_VECTOR(USARTC1_RXC_vect, SER_UART2)
|
|
USART_RXC_INTERRUPT_VECTOR(USARTD1_RXC_vect, SER_UART3)
|
|
USART_RXC_INTERRUPT_VECTOR(USARTE0_RXC_vect, SER_UART4)
|
|
#endif
|