241 lines
6.7 KiB
C
241 lines
6.7 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* \brief AT91SAM7S256 CRT.
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*/
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#include <io/arm.h>
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#include <cfg/macros.h>
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#define USE_FIXED_PLL 1
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#define XTAL_FREQ 18432000UL
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#if USE_FIXED_PLL
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#if CPU_FREQ != 48054857L
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/* Avoid errors on nightly test */
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#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
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#warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
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#endif
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#endif
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/*
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* With a 18.432MHz cristal, master clock is:
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* (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
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*/
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#define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
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#define PLL_DIV_VAL 14
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#define AT91MCK_PRES PMC_PRES_CLK_2
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#else /* !USE_FIXED_PLL*/
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#define PLL_IN_MIN 1000000UL
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#define PLL_IN_MAX 32000000UL
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#define PLL_OUT_MIN 80000000UL
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#define PLL_OUT_MAX 160000000UL
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#define DIV_HARD_MIN 1
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#define DIV_HARD_MAX 255
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#define DIV_MIN (DIV_ROUND(XTAL_FREQ, PLL_IN_MAX) \
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< DIV_HARD_MIN ? DIV_HARD_MIN : DIV_ROUND(XTAL_FREQ, PLL_IN_MAX))
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#define DIV_MAX (DIV_ROUND(XTAL_FREQ, PLL_IN_MIN) \
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> DIV_HARD_MAX ? DIV_HARD_MAX : DIV_ROUND(XTAL_FREQ, PLL_IN_MIN))
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#define MUL_MIN 0
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#define MUL_MAX 2047
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typedef struct PllRegs
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{
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uint32_t mul;
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uint32_t div;
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uint32_t pres;
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} PllRegs;
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/**
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* Code used to automatically compute the PLL registers.
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* Since the processor uses the internal 32kHz oscillator
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* this function takes a lot of time to be executed (~3s!).
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*/
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static const PllRegs pllCostants(void)
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{
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uint32_t best_err = CPU_FREQ;
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PllRegs res;
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for (uint32_t div = DIV_MIN; div <= DIV_MAX; div++)
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{
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for (uint32_t pres = 0; pres < 8; pres++)
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{
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uint32_t mul = DIV_ROUND((CPU_FREQ * div) << pres, XTAL_FREQ) - 1;
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if (mul <= MUL_MAX)
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{
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uint32_t pll = (XTAL_FREQ * (mul + 1)) / div;
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if (pll >= PLL_OUT_MIN && pll <= PLL_OUT_MAX)
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{
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uint32_t err = ABS((int32_t)((pll >> pres) - CPU_FREQ));
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if (err == 0)
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{
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res.div = div;
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res.mul = mul;
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res.pres = pres;
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return res;
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}
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if (err < best_err)
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{
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best_err = err;
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res.div = div;
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res.mul = mul;
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res.pres = pres;
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}
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}
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}
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}
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}
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return res;
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}
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#endif /* !USE_FIXED_PLL*/
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/*
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* Override dummy hardware init functions supplied by the ASM startup
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* routine.
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*/
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void __init1(void);
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void __init2(void);
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/**
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* Early hardware initialization routine1.
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* This will be called by the ASM CRT routine just
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* *before* clearing .bss and loading .data sections.
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* Usually only basic tasks are performed here (i.e. setting the PLL).
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* For more generic tasks, __init2() should be used.
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*
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* \note Please keep in mind that since .bss and .data are not yet set, care
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* must be taken. No static data can be used inside this funcition.
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* Also some libc functions or floating point operations could potentially
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* use initialized static data, be aware!
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*/
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void __init1(void)
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{
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/*
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* Compute number of master clock cycles in 1.5us.
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* Needed by flash writing functions.
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* The maximum FMCN value is 0xFF and 0 can be used only if
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* master clock is less than 33kHz.
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*/
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#define MCN DIV_ROUNDUP(CPU_FREQ, 666667UL)
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#define FMCN (CPU_FREQ <= 33333UL ? 0 : (MCN < 0xFF ? MCN : 0xFF))
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#if CPU_FREQ < 30000000UL
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/* Use 1 cycles for flash access. */
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MC_FMR = FMCN << MC_FMCN_SHIFT | MC_FWS_1R2W;
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#else
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/* Use 2 cycles for flash access. */
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MC_FMR = FMCN << MC_FMCN_SHIFT | MC_FWS_2R3W;
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#endif
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/* Disable all interrupts. Useful for debugging w/o target reset. */
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AIC_EOICR = 0xFFFFFFFF;
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AIC_IDCR = 0xFFFFFFFF;
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/* The watchdog is enabled after processor reset. Disable it. */
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WDT_MR = BV(WDT_WDDIS);
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/*
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* Enable the main oscillator. Set startup time of 6 * 8 slow
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* clock cycles and wait until oscillator is stabilized.
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*/
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CKGR_MOR = (6 << 8) | BV(CKGR_MOSCEN);
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while (!(PMC_SR & BV(PMC_MOSCS))) ;
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/* Switch to Slow oscillator clock. */
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PMC_MCKR &= ~PMC_CSS_MASK;
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while (!(PMC_SR & BV(PMC_MCKRDY))) ;
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/* Switch to prescaler div 1 factor. */
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PMC_MCKR &= ~PMC_PRES_MASK;
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while (!(PMC_SR & BV(PMC_MCKRDY))) ;
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uint32_t div, pres, mul;
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#if USE_FIXED_PLL
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div = PLL_DIV_VAL;
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mul = PLL_MUL_VAL;
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pres = AT91MCK_PRES;
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#else
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PllRegs pll = pllCostants();
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div = pll.div;
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mul = pll.mul;
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pres = pll.pres << PMC_PRES_SHIFT;
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#endif
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/*
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* Set PLL:
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* PLLfreq = crystal / divider * (multiplier + 1)
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* Wait 28 clock cycles until PLL is locked.
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*/
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CKGR_PLLR = ((mul << CKGR_MUL_SHIFT)
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| (28 << CKGR_PLLCOUNT_SHIFT) | div);
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while (!(PMC_SR & BV(PMC_LOCK))) ;
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/* Set master clock prescaler. */
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PMC_MCKR = pres;
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while (!(PMC_SR & BV(PMC_MCKRDY))) ;
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/*
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* Switch to PLL clock. Trying to set this together with the
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* prescaler fails (see datasheets).
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*/
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PMC_MCKR |= PMC_CSS_PLL_CLK;
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while (!(PMC_SR & BV(PMC_MCKRDY))) ;
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}
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/**
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* Early hardware initialization routine2.
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* This will be called by the ASM CRT routine just
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* *after* clearing .bss and loading .data sections and before calling main().
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*/
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void __init2(void)
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{
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/* Enable external reset key. */
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RSTC_MR = (RSTC_KEY | BV(RSTC_URSTEN));
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/* Enable clock for PIO(s) */
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PMC_PCER = BV(PIOA_ID);
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#if CPU_ARM_SAM7X
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PMC_PCER |= BV(PIOB_ID);
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#endif
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}
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