130 lines
3.3 KiB
C
130 lines
3.3 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* \brief LPC2378 CRT.
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* notest:arm
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*/
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#include <cpu/irq.h>
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#include <drv/vic_lpc2.h>
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#include <io/lpc23xx.h>
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#if CPU_FREQ != 72000000UL
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/* Avoid errors on nightly test */
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#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
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#warning Clock registers set for 72MHz operation, revise following code if you want a different clock.
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#endif
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#endif
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/*
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* With a 12MHz cristal, master clock is:
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* (((2 * 12 * (PLL_MUL_VAL + 1)) / (PLL_DIV_VAL + 1)) / (LPC2_CPUCLOCK_DIV + 1))= 72MHz
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*/
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#define PLL_MUL_VAL 11
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#define PLL_DIV_VAL 0
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#define LPC2_CPUCLOCK_DIV 3
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/* PLL feed sequence */
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#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)
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static void configurePll(void)
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{
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/* Disconnect and disable the PLL, if already active */
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if (PLLSTAT & (1 << 25))
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{
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/* Disconnect PLL, but leave it enabled */
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PLLCON = 0x01;
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PLL_FEED_SEQ();
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/* Disable PLL */
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PLLCON = 0;
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PLL_FEED_SEQ();
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}
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/* Enable the main oscillator and wait for it to be stable */
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SCS |= (1 << 5);
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while (!(SCS & (1 << 6))) ;
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/* Select the main oscillator as the PLL clock source */
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CLKSRCSEL = 0x01;
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/* Set up PLL mul and div */
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PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);
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PLL_FEED_SEQ();
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/* Enable PLL, disconnected */
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PLLCON = 0x01;
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PLL_FEED_SEQ();
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/* Set clock divider */
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CCLKCFG = LPC2_CPUCLOCK_DIV;
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/* Wait for the PLL to lock */
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while (!(PLLSTAT & (1 << 26))) ;
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/* Enable and connect the PLL */
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PLLCON = 0x03;
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PLL_FEED_SEQ();
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}
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void __init1(void);
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void __init1(void)
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{
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/* Map irq vectors to internal flash */
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MEMMAP = 0x01;
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/* Configure PLL, switch from IRC to Main OSC */
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configurePll();
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/* Set memory accelerator module flash timings */
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#if CPU_FREQ < 20000000UL
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MAMTIM = 1;
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#elif CPU_FREQ < 40000000UL
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MAMTIM = 2;
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#elif CPU_FREQ < 60000000UL
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MAMTIM = 3;
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#else
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MAMTIM = 4;
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#endif
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/* Memory accelerator module fully enabled */
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MAMCR = 0x02;
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}
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void __init2(void);
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void __init2(void)
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{
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vic_init();
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}
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