154 lines
8.7 KiB
C
154 lines
8.7 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* AT91 Memory controller.
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* This file is based on NUT/OS implementation. See license below.
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*/
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/*
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* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* For additional information see http://www.ethernut.de/
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*/
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#ifndef AT91_MC_H
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#define AT91_MC_H
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#define MC_RCR_OFF 0x00000000 ///< MC remap control register offset.
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#define MC_RCR (*((reg32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address.
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#define MC_RCB 0 ///< Remap command.
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#define MC_ASR_OFF 0x00000004 ///< MC abort status register offset.
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#define MC_ASR (*((reg32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address.
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#define MC_UNDADD 0 ///< Undefined Addess Abort status.
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#define MC_MISADD 1 ///< Misaligned Addess Abort status.
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#define MC_ABTSZ_MASK 0x00000300 ///< Abort size status mask.
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#define MC_ABTSZ_BYTE 0x00000000 ///< Byte size abort.
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#define MC_ABTSZ_HWORD 0x00000100 ///< Half-word size abort.
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#define MC_ABTSZ_WORD 0x00000200 ///< Word size abort.
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#define MC_ABTTYP_MASK 0x00000C00 ///< Abort type status mask.
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#define MC_ABTTYP_DATAR 0x00000000 ///< Data read abort.
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#define MC_ABTTYP_DATAW 0x00000400 ///< Data write abort.
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#define MC_ABTTYP_FETCH 0x00000800 ///< Code fetch abort.
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#define MC_MST_PDC 0x00020000 ///< PDC abort source.
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#define MC_MST_ARM 0x00040000 ///< ARM abort source.
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#define MC_SVMST_PDC 0x02000000 ///< Saved PDC abort source.
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#define MC_SVMST_ARM 0x04000000 ///< Saved ARM abort source.
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#define MC_AASR_OFF 0x00000008 ///< MC abort address status register offset.
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#define MC_AASR (*((reg32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address.
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#define MC_FMR_OFF 0x00000060 ///< MC flash mode register offset.
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#define MC_FMR (*((reg32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address.
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#define MC_FRDY 0 ///< Flash ready.
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#define MC_LOCKE 2 ///< Lock error.
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#define MC_PROGE 3 ///< Programming error.
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#define MC_NEBP 7 ///< No erase before programming.
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#define MC_FWS_MASK 0x00000300 ///< Flash wait state mask.
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#define MC_FWS_1R2W 0x00000000 ///< 1 cycle for read, 2 for write operations.
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#define MC_FWS_2R3W 0x00000100 ///< 2 cycles for read, 3 for write operations.
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#define MC_FWS_3R4W 0x00000200 ///< 3 cycles for read, 4 for write operations.
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#define MC_FWS_4R4W 0x00000300 ///< 4 cycles for read and write operations.
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#define MC_FMCN_MASK 0x00FF0000 ///< Flash microsecond cycle number mask.
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#define MC_FMCN_SHIFT 16 ///< Flash microsecond cycle number shift.
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#define MC_FCR_OFF 0x00000064 ///< MC flash command register offset.
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#define MC_FCR (*((reg32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address.
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#define MC_FCMD_MASK 0x0000000F ///< Flash command mask.
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#define MC_FCMD_NOP 0x00000000 ///< No command.
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#define MC_FCMD_WP 0x00000001 ///< Write page.
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#define MC_FCMD_SLB 0x00000002 ///< Set lock bit.
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#define MC_FCMD_WPL 0x00000003 ///< Write page and lock.
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#define MC_FCMD_CLB 0x00000004 ///< Clear lock bit.
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#define MC_FCMD_EA 0x00000008 ///< Erase all.
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#define MC_FCMD_SGPB 0x0000000B ///< Set general purpose NVM bit.
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#define MC_FCMD_CGPB 0x0000000D ///< Clear general purpose NVM bit.
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#define MC_FCMD_SSB 0x0000000F ///< Set security bit.
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#define MC_PAGEN_MASK 0x0003FF00 ///< Page number mask.
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#define MC_KEY 0x5A000000 ///< Writing protect key.
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#define MC_FSR_OFF 0x00000068 ///< MC flash status register offset.
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#define MC_FSR (*((reg32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address.
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#define MC_SECURITY 4 ///< Security bit status.
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#define MC_GPNVM0 8 ///< General purpose NVM bit 0.
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#define MC_GPNVM1 9 ///< General purpose NVM bit 1.
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#define MC_GPNVM2 10 ///< General purpose NVM bit 2.
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#define MC_LOCKS0 16 ///< Lock region 0 lock status.
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#define MC_LOCKS1 17 ///< Lock region 1 lock status.
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#define MC_LOCKS2 18 ///< Lock region 2 lock status.
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#define MC_LOCKS3 19 ///< Lock region 3 lock status.
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#define MC_LOCKS4 20 ///< Lock region 4 lock status.
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#define MC_LOCKS5 21 ///< Lock region 5 lock status.
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#define MC_LOCKS6 22 ///< Lock region 6 lock status.
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#define MC_LOCKS7 23 ///< Lock region 7 lock status.
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#define MC_LOCKS8 24 ///< Lock region 8 lock status.
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#define MC_LOCKS9 25 ///< Lock region 9 lock status.
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#define MC_LOCKS10 26 ///< Lock region 10 lock status.
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#define MC_LOCKS11 27 ///< Lock region 11 lock status.
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#define MC_LOCKS12 28 ///< Lock region 12 lock status.
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#define MC_LOCKS13 29 ///< Lock region 13 lock status.
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#define MC_LOCKS14 30 ///< Lock region 14 lock status.
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#define MC_LOCKS15 31 ///< Lock region 15 lock status.
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#endif /* AT91_MC_H */
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