195 lines
10 KiB
C
195 lines
10 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* AT91 power management controller.
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* This file is based on NUT/OS implementation. See license below.
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*/
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/*
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* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* For additional information see http://www.ethernut.de/
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*/
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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/** System Clock Enable, Disable and Status Register */
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/*\{*/
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#define PMC_SCER_OFF 0x00000000 ///< System clock enable register offset.
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#define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System clock enable register address.
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#define PMC_SCDR_OFF 0x00000004 ///< System clock disable register offset.
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#define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System clock disable register address.
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#define PMC_SCSR_OFF 0x00000008 ///< System clock status register offset.
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#define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System clock status register address.
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#define PMC_PCK 0 ///< Processor clock.
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#define PMC_UDP 7 ///< USB device port clock.
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#define PMC_PCK0 8 ///< Programmable clock 0 output.
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#define PMC_PCK1 9 ///< Programmable clock 1 output.
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#define PMC_PCK2 10 ///< Programmable clock 2 output.
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/*\}*/
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/** Peripheral Clock Enable, Disable and Status Register */
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/*\{*/
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#define PMC_PCER_OFF 0x00000010 ///< Peripheral clock enable register offset.
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#define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral clock enable register address.
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#define PMC_PCDR_OFF 0x00000014 ///< Peripheral clock disable register offset.
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#define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral clock disable register address.
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#define PMC_PCSR_OFF 0x00000018 ///< Peripheral clock status register offset.
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#define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral clock status register address.
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/*\}*/
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/** Clock Generator Main Oscillator Register */
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/*\{*/
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#define CKGR_MOR_OFF 0x00000020 ///< Main oscillator register offset.
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#define CKGR_MOR (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF))) ///< Main oscillator register address.
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#define CKGR_MOSCEN 0 ///< Main oscillator enable.
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#define CKGR_OSCBYPASS 1 ///< Main oscillator bypass.
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#define CKGR_OSCOUNT_MASK 0x0000FF00 ///< Main oscillator start-up time mask.
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#define CKGR_OSCOUNT_SHIFT 8 ///< Main oscillator start-up time LSB.
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/*\}*/
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/** Clock Generator Main Clock Frequency Register */
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/*\{*/
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#define CKGR_MCFR_OFF 0x00000024 ///< Main clock frequency register offset.
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#define CKGR_MCFR (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF))) ///< Main clock frequency register address.
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#define CKGR_MAINF_MASK 0x0000FFFF ///< Main clock frequency mask mask.
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#define CKGR_MAINRDY 16 ///< Main clock ready.
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/*\}*/
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/** PLL Registers */
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/*\{*/
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#define CKGR_PLLR_OFF 0x0000002C ///< Clock generator PLL register offset.
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#define CKGR_PLLR (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF))) ///< Clock generator PLL register address.
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#define CKGR_DIV_MASK 0x000000FF ///< Divider.
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#define CKGR_DIV_SHIFT 0 ///< Least significant bit of the divider.
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#define CKGR_DIV_0 0x00000000 ///< Divider output is 0.
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#define CKGR_DIV_BYPASS 0x00000001 ///< Divider is bypassed.
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#define CKGR_PLLCOUNT_MASK 0x00003F00 ///< PLL counter mask.
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#define CKGR_PLLCOUNT_SHIFT 8 ///< PLL counter LSB.
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#define CKGR_OUT_MASK 0x0000C000 ///< PLL output frequency range.
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#define CKGR_OUT_0 0x00000000 ///< Please refer to the PLL datasheet.
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#define CKGR_OUT_1 0x00004000 ///< Please refer to the PLL datasheet.
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#define CKGR_OUT_2 0x00008000 ///< Please refer to the PLL datasheet.
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#define CKGR_OUT_3 0x0000C000 ///< Please refer to the PLL datasheet.
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#define CKGR_MUL_MASK 0x07FF0000 ///< PLL multiplier.
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#define CKGR_MUL_SHIFT 16 ///< Least significant bit of the PLL multiplier.
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#define CKGR_USBDIV_MASK 0x30000000 ///< Divider for USB clocks.
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#define CKGR_USBDIV_1 0x00000000 ///< Divider output is PLL clock output.
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#define CKGR_USBDIV_2 0x10000000 ///< Divider output is PLL clock output divided by 2.
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#define CKGR_USBDIV_4 0x20000000 ///< Divider output is PLL clock output divided by 4.
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/*\}*/
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/** Master Clock Register */
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/*\{*/
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#define PMC_MCKR_OFF 0x00000030 ///< Master clock register offset.
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#define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master clock register address.
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#define PMC_PCKR0_OFF 0x00000040 ///< Programmable clock 0 register offset.
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#define PMC_PCKR0 (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF))) ///< Programmable clock 0 register address.
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#define PMC_PCKR1_OFF 0x00000044 ///< Programmable clock 1 register offset.
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#define PMC_PCKR1 (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF))) ///< Programmable clock 1 register address.
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#define PMC_PCKR2_OFF 0x00000048 ///< Programmable clock 2 register offset.
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#define PMC_PCKR2 (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF))) ///< Programmable clock 2 register address.
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#define PMC_CSS_MASK 0x00000003 ///< Clock selection mask.
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#define PMC_CSS_SLOW_CLK 0x00000000 ///< Slow clock selected.
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#define PMC_CSS_MAIN_CLK 0x00000001 ///< Main clock selected.
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#define PMC_CSS_PLL_CLK 0x00000003 ///< PLL clock selected.
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#define PMC_PRES_MASK 0x0000001C ///< Clock prescaler mask.
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#define PMC_PRES_SHIFT 2 ///< Clock prescaler LSB.
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#define PMC_PRES_CLK 0x00000000 ///< Selected clock, not divided.
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#define PMC_PRES_CLK_2 0x00000004 ///< Selected clock divided by 2.
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#define PMC_PRES_CLK_4 0x00000008 ///< Selected clock divided by 4.
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#define PMC_PRES_CLK_8 0x0000000C ///< Selected clock divided by 8.
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#define PMC_PRES_CLK_16 0x00000010 ///< Selected clock divided by 16.
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#define PMC_PRES_CLK_32 0x00000014 ///< Selected clock divided by 32.
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#define PMC_PRES_CLK_64 0x00000018 ///< Selected clock divided by 64.
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/*\}*/
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/** Power Management Status and Interrupt Registers */
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/*\{*/
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#define PMC_IER_OFF 0x00000060 ///< Interrupt enable register offset.
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#define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF))) ///< Interrupt enable register address.
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#define PMC_IDR_OFF 0x00000064 ///< Interrupt disable register offset.
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#define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF))) ///< Interrupt disable register address.
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#define PMC_SR_OFF 0x00000068 ///< Status register offset.
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#define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF))) ///< Status register address.
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#define PMC_IMR_OFF 0x0000006C ///< Interrupt mask register offset.
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#define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF))) ///< Interrupt mask register address.
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#define PMC_MOSCS 0 ///< Main oscillator.
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#define PMC_LOCK 2 ///< PLL lock.
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#define PMC_MCKRDY 3 ///< Master clock ready.
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#define PMC_PCKRDY0 8 ///< Programmable clock 0 ready.
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#define PMC_PCKRDY1 9 ///< Programmable clock 1 ready.
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#define PMC_PCKRDY2 10 ///< Programmable clock 2 ready.
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/*\}*/
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#endif /* AT91_PMC_H */
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