412 lines
8.7 KiB
C
412 lines
8.7 KiB
C
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief Driver for the AVR ATMega TWI (implementation)
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*
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* \author Stefano Fedrigo <aleph@develer.com>
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* \author Bernie Innocenti <bernie@codewiz.org>
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* \author Daniele Basile <asterix@develer.com>
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*/
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#include "cfg/cfg_i2c.h"
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#include <hw/hw_cpufreq.h> /* CPU_FREQ */
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#define LOG_LEVEL I2C_LOG_LEVEL
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#define LOG_FORMAT I2C_LOG_FORMAT
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#include <cfg/log.h>
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#include <cfg/debug.h>
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#include <cfg/macros.h> // BV()
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#include <cfg/module.h>
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#include <cpu/detect.h>
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#include <cpu/irq.h>
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#include <drv/timer.h>
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#include <drv/i2c.h>
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#include <cpu/power.h>
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#include <compat/twi.h>
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#if !CONFIG_I2C_DISABLE_OLD_API
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/* Wait for TWINT flag set: bus is ready */
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#define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
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/**
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* Send START condition on the bus.
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*
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* \return true on success, false otherwise.
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*/
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static bool i2c_builtin_start(void)
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{
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TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
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WAIT_TWI_READY;
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if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
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return true;
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LOG_ERR("!TW_(REP)START: %x\n", TWSR);
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return false;
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}
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/**
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* Send START condition and select slave for write.
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* \c id is the device id comprehensive of address left shifted by 1.
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* The LSB of \c id is ignored and reset to 0 for write operation.
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*
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* \return true on success, false otherwise.
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*/
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bool i2c_builtin_start_w(uint8_t id)
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{
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/*
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* Loop on the select write sequence: when the eeprom is busy
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* writing previously sent data it will reply to the SLA_W
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* control byte with a NACK. In this case, we must
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* keep trying until the eeprom responds with an ACK.
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*/
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ticks_t start = timer_clock();
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while (i2c_builtin_start())
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{
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TWDR = id & ~I2C_READBIT;
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TWCR = BV(TWINT) | BV(TWEN);
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WAIT_TWI_READY;
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if (TW_STATUS == TW_MT_SLA_ACK)
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return true;
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else if (TW_STATUS != TW_MT_SLA_NACK)
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{
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LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
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break;
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}
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else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
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{
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LOG_ERR("Timeout on TWI_MT_START\n");
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break;
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}
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}
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return false;
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}
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/**
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* Send START condition and select slave for read.
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* \c id is the device id comprehensive of address left shifted by 1.
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* The LSB of \c id is ignored and set to 1 for read operation.
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*
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* \return true on success, false otherwise.
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*/
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bool i2c_builtin_start_r(uint8_t id)
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{
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if (i2c_builtin_start())
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{
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TWDR = id | I2C_READBIT;
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TWCR = BV(TWINT) | BV(TWEN);
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WAIT_TWI_READY;
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if (TW_STATUS == TW_MR_SLA_ACK)
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return true;
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LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
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}
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return false;
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}
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/**
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* Send STOP condition.
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*/
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void i2c_builtin_stop(void)
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{
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TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
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}
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/**
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* Put a single byte in master transmitter mode
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* to the selected slave device through the TWI bus.
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*
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* \return true on success, false on error.
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*/
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bool i2c_builtin_put(const uint8_t data)
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{
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TWDR = data;
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TWCR = BV(TWINT) | BV(TWEN);
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WAIT_TWI_READY;
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if (TW_STATUS != TW_MT_DATA_ACK)
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{
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LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
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return false;
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}
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return true;
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}
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/**
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* Get 1 byte from slave in master transmitter mode
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* to the selected slave device through the TWI bus.
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* If \a ack is true issue a ACK after getting the byte,
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* otherwise a NACK is issued.
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*
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* \return the byte read if ok, EOF on errors.
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*/
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int i2c_builtin_get(bool ack)
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{
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TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
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WAIT_TWI_READY;
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if (ack)
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{
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if (TW_STATUS != TW_MR_DATA_ACK)
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{
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LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
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return EOF;
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}
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}
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else
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{
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if (TW_STATUS != TW_MR_DATA_NACK)
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{
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LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
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return EOF;
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}
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}
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/* avoid sign extension */
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return (int)(uint8_t)TWDR;
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}
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#endif /* !CONFIG_I2C_DISABLE_OLD_API */
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/*
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* New Api
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*/
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struct I2cHardware
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{
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};
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/* Wait for TWINT flag set: bus is ready */
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#define WAIT_READY() \
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do { \
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while (!(TWCR & BV(TWINT))) \
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cpu_relax(); \
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} while (0)
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/**
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* Send START condition on the bus.
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*/
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INLINE bool i2c_hw_start(void)
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{
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TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
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WAIT_READY();
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if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
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return true;
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return false;
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}
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/**
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* Send STOP condition.
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*/
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INLINE void i2c_hw_stop(void)
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{
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TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
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}
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static void i2c_avr_start(I2c *i2c, uint16_t slave_addr)
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{
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/*
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* Loop on the select write sequence: when the eeprom is busy
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* writing previously sent data it will reply to the SLA_W
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* control byte with a NACK. In this case, we must
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* keep trying until the slave responds with an ACK.
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*/
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ticks_t start = timer_clock();
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while (i2c_hw_start())
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{
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uint8_t sla_ack = 0;
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uint8_t sla_nack = 0;
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if (I2C_TEST_START(i2c->flags) == I2C_START_W)
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{
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TWDR = slave_addr & ~I2C_READBIT;
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sla_ack = TW_MT_SLA_ACK;
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sla_nack = TW_MT_SLA_NACK;
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}
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else
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{
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TWDR = slave_addr | I2C_READBIT;
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sla_ack = TW_MR_SLA_ACK;
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sla_nack = TW_MR_SLA_NACK;
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}
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TWCR = BV(TWINT) | BV(TWEN);
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WAIT_READY();
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if (TW_STATUS == sla_ack)
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return;
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else if (TW_STATUS != sla_nack)
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{
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LOG_ERR("Start addr NACK[%x]\n", TWSR);
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i2c->errors |= I2C_NO_ACK;
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i2c_hw_stop();
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break;
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}
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else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
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{
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LOG_ERR("Start timeout\n");
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i2c->errors |= I2C_START_TIMEOUT;
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i2c_hw_stop();
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break;
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}
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}
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LOG_ERR("I2c error\n");
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i2c->errors |= I2C_ERR;
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i2c_hw_stop();
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}
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static void i2c_avr_putc(I2c *i2c, const uint8_t data)
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{
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TWDR = data;
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TWCR = BV(TWINT) | BV(TWEN);
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WAIT_READY();
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if (TW_STATUS != TW_MT_DATA_ACK)
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{
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LOG_ERR("Data nack[%x]\n", TWSR);
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i2c->errors |= I2C_DATA_NACK;
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i2c_hw_stop();
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}
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if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
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i2c_hw_stop();
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}
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static uint8_t i2c_avr_getc(I2c *i2c)
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{
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uint8_t data_flag = 0;
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if (i2c->xfer_size == 1)
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{
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TWCR = BV(TWINT) | BV(TWEN);
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data_flag = TW_MR_DATA_NACK;
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}
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else
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{
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TWCR = BV(TWINT) | BV(TWEN) | BV(TWEA);
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data_flag = TW_MR_DATA_ACK;
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}
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WAIT_READY();
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if (TW_STATUS != data_flag)
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{
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LOG_ERR("Data nack[%x]\n", TWSR);
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i2c->errors |= I2C_DATA_NACK;
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i2c_hw_stop();
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return 0xFF;
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}
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uint8_t data = TWDR;
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if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
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i2c_hw_stop();
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return data;
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}
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static const I2cVT i2c_avr_vt =
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{
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.start = i2c_avr_start,
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.getc = i2c_avr_getc,
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.putc = i2c_avr_putc,
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.write = i2c_genericWrite,
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.read = i2c_genericRead,
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};
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struct I2cHardware i2c_avr_hw[] =
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{
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{ /* I2C0 */
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},
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};
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/**
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* Initialize I2C module.
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*/
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void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
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{
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i2c->hw = &i2c_avr_hw[dev];
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i2c->vt = &i2c_avr_vt;
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ATOMIC(
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/*
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* This is pretty useless according to AVR's datasheet,
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* but it helps us driving the TWI data lines on boards
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* where the bus pull-up resistors are missing. This is
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* probably due to some unwanted interaction between the
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* port pin and the TWI lines.
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*/
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#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
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PORTD |= BV(PD0) | BV(PD1);
|
||
|
|
DDRD |= BV(PD0) | BV(PD1);
|
||
|
|
#elif CPU_AVR_ATMEGA8
|
||
|
|
PORTC |= BV(PC4) | BV(PC5);
|
||
|
|
DDRC |= BV(PC4) | BV(PC5);
|
||
|
|
#elif CPU_AVR_ATMEGA32
|
||
|
|
PORTC |= BV(PC1) | BV(PC0);
|
||
|
|
DDRC |= BV(PC1) | BV(PC0);
|
||
|
|
#else
|
||
|
|
#error Unsupported architecture
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set speed:
|
||
|
|
* F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
|
||
|
|
*/
|
||
|
|
ASSERT(clock);
|
||
|
|
#define TWI_PRESC 1 /* 4 ^ TWPS */
|
||
|
|
|
||
|
|
TWBR = (CPU_FREQ / (2 * clock * TWI_PRESC)) - (8 / TWI_PRESC);
|
||
|
|
TWSR = 0;
|
||
|
|
TWCR = BV(TWEN);
|
||
|
|
);
|
||
|
|
}
|