Updated buffer lengths

This commit is contained in:
Mark Qvist 2019-01-08 13:19:58 +01:00
parent 00dcf5a300
commit 42dcd121cc
4 changed files with 21 additions and 22 deletions

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@ -38,13 +38,6 @@ inline static uint8_t sinSample(uint16_t i) {
#define CPU_FREQ F_CPU #define CPU_FREQ F_CPU
#define CONFIG_AFSK_RX_BUFLEN CONFIG_ADC_SAMPLERATE/150
#define CONFIG_AFSK_TX_BUFLEN CONFIG_ADC_SAMPLERATE/150
#define CONFIG_AFSK_RXTIMEOUT 0
#define CONFIG_AFSK_TXWAIT 0UL
#define CONFIG_AFSK_PREAMBLE_LEN 150UL
#define CONFIG_AFSK_TRAILER_LEN 25UL
#define BIT_STUFF_LEN 5
#define BITRATE 1200 #define BITRATE 1200
@ -59,6 +52,15 @@ inline static uint8_t sinSample(uint16_t i) {
#define CONFIG_DAC_SAMPLERATE 38400UL #define CONFIG_DAC_SAMPLERATE 38400UL
#endif #endif
#define CONFIG_AFSK_RX_BUFLEN CONFIG_ADC_SAMPLERATE/75
#define CONFIG_AFSK_TX_BUFLEN CONFIG_ADC_SAMPLERATE/75
#define CONFIG_AFSK_RXTIMEOUT 0
#define CONFIG_AFSK_PREAMBLE_LEN 150UL
#define CONFIG_AFSK_TRAILER_LEN 25UL
#define BIT_STUFF_LEN 5
#define ADC_SAMPLESPERBIT (CONFIG_ADC_SAMPLERATE / BITRATE) #define ADC_SAMPLESPERBIT (CONFIG_ADC_SAMPLERATE / BITRATE)
#define ADC_TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_ADC_SAMPLERATE) - 1) #define ADC_TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_ADC_SAMPLERATE) - 1)
@ -169,9 +171,6 @@ typedef struct Afsk
uint16_t silentSamples; // How many samples were completely silent uint16_t silentSamples; // How many samples were completely silent
FIFOBuffer txFifo; // FIFO for transmit data
uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actual data storage for said FIFO
volatile bool sending; // Set when modem is sending volatile bool sending; // Set when modem is sending
volatile bool sending_data; // Set when modem is sending data volatile bool sending_data; // Set when modem is sending data
@ -188,6 +187,9 @@ typedef struct Afsk
FIFOBuffer rxFifo; // FIFO for received data FIFOBuffer rxFifo; // FIFO for received data
uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
FIFOBuffer txFifo; // FIFO for transmit data
uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actual data storage for said FIFO
int16_t iirX[2]; // IIR Filter X cells int16_t iirX[2]; // IIR Filter X cells
int16_t iirY[2]; // IIR Filter Y cells int16_t iirY[2]; // IIR Filter Y cells

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@ -19,7 +19,6 @@ void serial_init(Serial *serial) {
UCSR0B = _BV(RXEN0) | _BV(TXEN0); UCSR0B = _BV(RXEN0) | _BV(TXEN0);
FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, uart0_getchar, _FDEV_SETUP_RW); FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, uart0_getchar, _FDEV_SETUP_RW);
//FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, NULL, _FDEV_SETUP_WRITE);
serial->uart0 = uart0_fd; serial->uart0 = uart0_fd;
} }

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@ -32,9 +32,6 @@ void ax25_poll(AX25Ctx *ctx) {
if (!ctx->escape && c == HDLC_FLAG) { if (!ctx->escape && c == HDLC_FLAG) {
if (ctx->frame_len >= AX25_MIN_FRAME_LEN) { if (ctx->frame_len >= AX25_MIN_FRAME_LEN) {
if (ctx->crc_in == AX25_CRC_CORRECT || CONFIG_PASSALL) { if (ctx->crc_in == AX25_CRC_CORRECT || CONFIG_PASSALL) {
#if OPEN_SQUELCH == true
LED_RX_ON();
#endif
ax25_decode(ctx); ax25_decode(ctx);
} }
} }

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@ -53,13 +53,14 @@ void kiss_messageCallback(AX25Ctx *ctx) {
void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) { void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
bool sent = false; bool sent = false;
if (CONFIG_AFSK_TXWAIT > 0) { // TODO: Determine if this is to be removed
ticks_t wait_start = timer_clock(); // if (CONFIG_AFSK_TXWAIT > 0) {
long wait_ticks = ms_to_ticks(CONFIG_AFSK_TXWAIT); // ticks_t wait_start = timer_clock();
while (timer_clock() - wait_start < wait_ticks) { // long wait_ticks = ms_to_ticks(CONFIG_AFSK_TXWAIT);
cpu_relax(); // while (timer_clock() - wait_start < wait_ticks) {
} // cpu_relax();
} // }
// }
while (!sent) { while (!sent) {
if(CONFIG_FULL_DUPLEX || !channel->hdlc.dcd) { if(CONFIG_FULL_DUPLEX || !channel->hdlc.dcd) {
uint8_t tp = rand() & 0xFF; uint8_t tp = rand() & 0xFF;