Updated buffer lengths
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@ -38,13 +38,6 @@ inline static uint8_t sinSample(uint16_t i) {
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#define CPU_FREQ F_CPU
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#define CPU_FREQ F_CPU
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#define CONFIG_AFSK_RX_BUFLEN CONFIG_ADC_SAMPLERATE/150
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#define CONFIG_AFSK_TX_BUFLEN CONFIG_ADC_SAMPLERATE/150
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#define CONFIG_AFSK_RXTIMEOUT 0
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#define CONFIG_AFSK_TXWAIT 0UL
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#define CONFIG_AFSK_PREAMBLE_LEN 150UL
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#define CONFIG_AFSK_TRAILER_LEN 25UL
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#define BIT_STUFF_LEN 5
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#define BITRATE 1200
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#define BITRATE 1200
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@ -59,6 +52,15 @@ inline static uint8_t sinSample(uint16_t i) {
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#define CONFIG_DAC_SAMPLERATE 38400UL
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#define CONFIG_DAC_SAMPLERATE 38400UL
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#endif
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#endif
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#define CONFIG_AFSK_RX_BUFLEN CONFIG_ADC_SAMPLERATE/75
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#define CONFIG_AFSK_TX_BUFLEN CONFIG_ADC_SAMPLERATE/75
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#define CONFIG_AFSK_RXTIMEOUT 0
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#define CONFIG_AFSK_PREAMBLE_LEN 150UL
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#define CONFIG_AFSK_TRAILER_LEN 25UL
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#define BIT_STUFF_LEN 5
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#define ADC_SAMPLESPERBIT (CONFIG_ADC_SAMPLERATE / BITRATE)
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#define ADC_SAMPLESPERBIT (CONFIG_ADC_SAMPLERATE / BITRATE)
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#define ADC_TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_ADC_SAMPLERATE) - 1)
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#define ADC_TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_ADC_SAMPLERATE) - 1)
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@ -169,9 +171,6 @@ typedef struct Afsk
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uint16_t silentSamples; // How many samples were completely silent
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uint16_t silentSamples; // How many samples were completely silent
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FIFOBuffer txFifo; // FIFO for transmit data
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uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actual data storage for said FIFO
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volatile bool sending; // Set when modem is sending
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volatile bool sending; // Set when modem is sending
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volatile bool sending_data; // Set when modem is sending data
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volatile bool sending_data; // Set when modem is sending data
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@ -188,6 +187,9 @@ typedef struct Afsk
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FIFOBuffer rxFifo; // FIFO for received data
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FIFOBuffer rxFifo; // FIFO for received data
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uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
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uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
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FIFOBuffer txFifo; // FIFO for transmit data
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uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actual data storage for said FIFO
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int16_t iirX[2]; // IIR Filter X cells
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int16_t iirX[2]; // IIR Filter X cells
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int16_t iirY[2]; // IIR Filter Y cells
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int16_t iirY[2]; // IIR Filter Y cells
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@ -19,7 +19,6 @@ void serial_init(Serial *serial) {
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UCSR0B = _BV(RXEN0) | _BV(TXEN0);
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UCSR0B = _BV(RXEN0) | _BV(TXEN0);
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FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, uart0_getchar, _FDEV_SETUP_RW);
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FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, uart0_getchar, _FDEV_SETUP_RW);
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//FILE uart0_fd = FDEV_SETUP_STREAM(uart0_putchar, NULL, _FDEV_SETUP_WRITE);
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serial->uart0 = uart0_fd;
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serial->uart0 = uart0_fd;
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}
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}
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@ -32,9 +32,6 @@ void ax25_poll(AX25Ctx *ctx) {
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if (!ctx->escape && c == HDLC_FLAG) {
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if (!ctx->escape && c == HDLC_FLAG) {
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if (ctx->frame_len >= AX25_MIN_FRAME_LEN) {
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if (ctx->frame_len >= AX25_MIN_FRAME_LEN) {
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if (ctx->crc_in == AX25_CRC_CORRECT || CONFIG_PASSALL) {
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if (ctx->crc_in == AX25_CRC_CORRECT || CONFIG_PASSALL) {
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#if OPEN_SQUELCH == true
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LED_RX_ON();
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#endif
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ax25_decode(ctx);
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ax25_decode(ctx);
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}
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}
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}
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}
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@ -53,13 +53,14 @@ void kiss_messageCallback(AX25Ctx *ctx) {
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void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
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void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
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bool sent = false;
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bool sent = false;
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if (CONFIG_AFSK_TXWAIT > 0) {
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// TODO: Determine if this is to be removed
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ticks_t wait_start = timer_clock();
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// if (CONFIG_AFSK_TXWAIT > 0) {
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long wait_ticks = ms_to_ticks(CONFIG_AFSK_TXWAIT);
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// ticks_t wait_start = timer_clock();
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while (timer_clock() - wait_start < wait_ticks) {
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// long wait_ticks = ms_to_ticks(CONFIG_AFSK_TXWAIT);
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cpu_relax();
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// while (timer_clock() - wait_start < wait_ticks) {
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}
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// cpu_relax();
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}
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// }
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// }
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while (!sent) {
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while (!sent) {
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if(CONFIG_FULL_DUPLEX || !channel->hdlc.dcd) {
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if(CONFIG_FULL_DUPLEX || !channel->hdlc.dcd) {
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uint8_t tp = rand() & 0xFF;
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uint8_t tp = rand() & 0xFF;
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