Before PLL algo adjust
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@ -83,7 +83,7 @@ INLINE uint8_t sinSample(uint16_t i) {
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#define PHASE_BITS 8
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#define PHASE_INC 1 // FIXME: originally 1
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#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS)
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#define PHASE_THRESHOLD (PHASE_MAX / 4) + (PHASE_MAX / 8) // FIXME: originally /2
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#define PHASE_THRESHOLD (PHASE_MAX / 4) // FIXME: originally /2
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// Modulation constants
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#define MARK_FREQ 1200
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@ -348,7 +348,7 @@ void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
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}
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}
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// We incroment our phase counter
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// We increment our phase counter
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afsk->currentPhase += PHASE_BITS;
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// Check if we have reached the end of
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@ -103,7 +103,7 @@ int main(void)
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// and the byte is not a "transmit" (newline) character,
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// we should store it for transmission.
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if ((serialLen < MP1_MAX_FRAME_LENGTH) && (sbyte != 138)) {
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kprintf("Byte: %d\n", sbyte);
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//kprintf("Byte: %d\n", sbyte); // FIXME: delete
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// Put the read byte into the buffer;
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serialBuffer[serialLen] = sbyte;
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// Increment the read length counter
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@ -1,2 +1,2 @@
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#define VERS_BUILD 477
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#define VERS_BUILD 480
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#define VERS_HOST "vixen"
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