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Migrated HDLC

This commit is contained in:
Mark Qvist 2014-04-04 00:06:02 +02:00
parent 16fd081e4b
commit 66ab74fca7
2 changed files with 28 additions and 30 deletions
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56
Modem/afsk.c
View File

@ -62,23 +62,18 @@ STATIC_ASSERT(!(CONFIG_AFSK_DAC_SAMPLERATE % BITRATE));
#define DAC_SAMPLESPERBIT (CONFIG_AFSK_DAC_SAMPLERATE / BITRATE) #define DAC_SAMPLESPERBIT (CONFIG_AFSK_DAC_SAMPLERATE / BITRATE)
static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo) static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo) {
{
bool ret = true; bool ret = true;
hdlc->demodulatedBits <<= 1; hdlc->demodulatedBits <<= 1;
hdlc->demodulatedBits |= bit ? 1 : 0; hdlc->demodulatedBits |= bit ? 1 : 0;
/* HDLC Flag */ // Check if we have received a HDLC flag (01111110)
if (hdlc->demodulatedBits == HDLC_FLAG) if (hdlc->demodulatedBits == HDLC_FLAG) {
{ if (!fifo_isfull(fifo)) {
if (!fifo_isfull(fifo))
{
fifo_push(fifo, HDLC_FLAG); fifo_push(fifo, HDLC_FLAG);
hdlc->receiving = true; hdlc->receiving = true;
} } else {
else
{
ret = false; ret = false;
hdlc->receiving = false; hdlc->receiving = false;
} }
@ -88,56 +83,59 @@ static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
return ret; return ret;
} }
/* Reset */ // Check if we have received a RESET flag (01111111)
if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET) if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET) {
{
hdlc->receiving = false; hdlc->receiving = false;
return ret; return ret;
} }
// If we are just receiving noise, don't bother with anything
if (!hdlc->receiving) if (!hdlc->receiving)
return ret; return ret;
/* Stuffed bit */ // First check if what we are seeing is a stuffed bit
if ((hdlc->demodulatedBits & 0x3f) == 0x3e) if ((hdlc->demodulatedBits & 0x3f) == 0x3e)
return ret; return ret;
// If we have an actual 1 bit, push this to the current byte
if (hdlc->demodulatedBits & 0x01) if (hdlc->demodulatedBits & 0x01)
hdlc->currentByte |= 0x80; hdlc->currentByte |= 0x80;
if (++hdlc->bitIndex >= 8) // Increment the bitIndex and check if we have a complete byte
{ if (++hdlc->bitIndex >= 8) {
if ((hdlc->currentByte == HDLC_FLAG // If we have a HDLC control character,
|| hdlc->currentByte == HDLC_RESET // put a AX.25 escape in the received data
|| hdlc->currentByte == AX25_ESC)) if ((hdlc->currentByte == HDLC_FLAG ||
{ hdlc->currentByte == HDLC_RESET ||
if (!fifo_isfull(fifo)) hdlc->currentByte == AX25_ESC)) {
if (!fifo_isfull(fifo)) {
fifo_push(fifo, AX25_ESC); fifo_push(fifo, AX25_ESC);
else } else {
{
hdlc->receiving = false; hdlc->receiving = false;
ret = false; ret = false;
} }
} }
if (!fifo_isfull(fifo)) // Push the actual byte to the received data FIFO
if (!fifo_isfull(fifo)) {
fifo_push(fifo, hdlc->currentByte); fifo_push(fifo, hdlc->currentByte);
else } else {
{
hdlc->receiving = false; hdlc->receiving = false;
ret = false; ret = false;
} }
hdlc->currentByte = 0; hdlc->currentByte = 0;
hdlc->bitIndex = 0; hdlc->bitIndex = 0;
}
else } else {
// We don't have a full byte yet, bitshift the byte
// to make room for the next bit
hdlc->currentByte >>= 1; hdlc->currentByte >>= 1;
}
return ret; return ret;
} }
void afsk_adc_isr(Afsk *afsk, int8_t currentSample) { void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
// To determine the received frequency, and thereby // To determine the received frequency, and thereby
// the bit of the sample, we multiply the sample by // the bit of the sample, we multiply the sample by

2
buildrev.h
View File

@ -1,2 +1,2 @@
#define VERS_BUILD 81 #define VERS_BUILD 93
#define VERS_HOST "vixen" #define VERS_HOST "vixen"