Filter work
This commit is contained in:
Mark Qvist
parent
56bed68143
commit
874689c602
1
device.h
1
device.h
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@ -14,6 +14,7 @@
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// Sampling & timer setup
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#define CONFIG_SAMPLERATE 19200UL
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//#define CONFIG_SAMPLERATE 9600UL
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// Serial settings
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#define BAUD 115200
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@ -376,45 +376,68 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
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afsk->iirX[0] = afsk->iirX[1];
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#if CONFIG_SAMPLERATE == 9600
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#if FILTER_CUTOFF == 600
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) >> 2;
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// The above is a simplification of:
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// afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / 3.558147322;
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#else
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#error Unsupported filter cutoff!
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#endif
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#elif CONFIG_SAMPLERATE == 19200
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#if FILTER_CUTOFF == 600
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / 6;
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#else
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#error Unsupported filter cutoff!
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#endif
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#else
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#error Unsupported samplerate!
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#endif
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afsk->iirY[0] = afsk->iirY[1];
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#if CONFIG_SAMPLERATE == 9600
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#if FILTER_CUTOFF == 600
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] >> 1);
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// The above is a simplification of:
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// afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] * 0.4379097269);
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#else
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#error Unsupported filter cutoff!
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#endif
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#elif CONFIG_SAMPLERATE == 19200
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#if FILTER_CUTOFF == 600
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#if FILTER_CUTOFF == 500
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#define IIR_GAIN 4 // Really 4.082041675
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#define IIR_POLE 2 // Really Y[0] * 0.5100490981
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / 2);
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#else
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#error Unsupported filter cutoff!
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#endif
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#elif CONFIG_SAMPLERATE == 19200
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#if FILTER_CUTOFF == 150
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#define IIR_GAIN 2 // Really 2.172813446e
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#define IIR_POLE 2 // Really Y[0] * 0.9079534415
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#elif FILTER_CUTOFF == 500
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#define IIR_GAIN 7 // Really 5.006847792
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#define IIR_POLE 2 // Really Y[0] * 0.6005470741
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#elif FILTER_CUTOFF == 600
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#define IIR_GAIN 6 // Really 6.166411713
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#define IIR_POLE 2 // Really Y[0] * 0.6756622663
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#elif FILTER_CUTOFF == 772
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#define IIR_GAIN 5 // Really 5.006847792
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#define IIR_POLE 2 // Really Y[0] * 0.6005470741
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#elif FILTER_CUTOFF == 1000
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#define IIR_GAIN 4 // Really 4.082041675
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#define IIR_POLE 2 // Really Y[0] * 0.5100490981
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#elif FILTER_CUTOFF == 1400
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#define IIR_GAIN 3 // Really 3.182326364
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#define IIR_POLE 3 // Really Y[0] * 0.3715289474
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afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / IIR_GAIN;
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afsk->iirY[0] = afsk->iirY[1];
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afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + (afsk->iirY[0] / IIR_POLE);
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#else
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#error Unsupported filter cutoff!
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#endif
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#else
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#error Unsupported samplerate!
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#error No filters defined for specified samplerate!
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#endif
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//int8_t freq_disc = (int8_t)fifo_pop(&afsk->delayFifo) * currentSample;
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// We put the sampled bit in a delay-line:
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// First we bitshift everything 1 left
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afsk->sampledBits <<= 1;
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@ -552,15 +575,12 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
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ISR(ADC_vect) {
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TIFR1 = _BV(ICF1);
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//DAC_PORT ^= 0xFF;
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//DAC_PORT = ADCH;
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AFSK_adc_isr(AFSK_modem, (ADCH - 128));
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if (hw_afsk_dac_isr) {
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DAC_PORT = AFSK_dac_isr(AFSK_modem);
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LED_TX_ON();
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} else {
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// TODO: Enable full duplex if possible
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AFSK_adc_isr(AFSK_modem, (ADCH - 128));
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DAC_PORT = 127;
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LED_TX_OFF();
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}
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@ -569,6 +589,10 @@ ISR(ADC_vect) {
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/*
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// TODO: Remove these debug sample collection functions
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//DAC_PORT ^= 0xFF;
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//DAC_PORT = ADCH;
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if (capturedsamples == SAMPLES_TO_CAPTURE) {
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printf("--- Dumping samples ---");
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for (ticks_t i = 0; i < SAMPLES_TO_CAPTURE; i++) {
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@ -11,7 +11,7 @@
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#include "protocol/HDLC.h"
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#define SIN_LEN 512
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static const uint8_t sin_table[] PROGMEM =
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static const uint8_t sine_table[] =
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{
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128, 129, 131, 132, 134, 135, 137, 138, 140, 142, 143, 145, 146, 148, 149, 151,
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152, 154, 155, 157, 158, 160, 162, 163, 165, 166, 167, 169, 170, 172, 173, 175,
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@ -26,7 +26,7 @@ static const uint8_t sin_table[] PROGMEM =
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inline static uint8_t sinSample(uint16_t i) {
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uint16_t newI = i % (SIN_LEN/2);
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newI = (newI >= (SIN_LEN/4)) ? (SIN_LEN/2 - newI -1) : newI;
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uint8_t sine = pgm_read_byte(&sin_table[newI]);
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uint8_t sine = sine_table[newI];
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return (i >= (SIN_LEN/2)) ? (255 - sine) : sine;
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}
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@ -34,12 +34,8 @@ inline static uint8_t sinSample(uint16_t i) {
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#define SWITCH_TONE(inc) (((inc) == MARK_INC) ? SPACE_INC : MARK_INC)
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#define BITS_DIFFER(bits1, bits2) (((bits1)^(bits2)) & 0x01)
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#define TRANSITION_FOUND(bits) BITS_DIFFER((bits), (bits) >> 1)
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// TODO: Maybe revert to only looking at two samples
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#define DUAL_XOR(bits1, bits2) ((((bits1)^(bits2)) & 0x03) == 0x03)
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#define QUAD_XOR(bits1, bits2) ((((bits1)^(bits2)) & 0x0F) == 0x0F)
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#define SIGNAL_TRANSITIONED(bits) QUAD_XOR((bits), (bits) >> 4)
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// #define SIGNAL_TRANSITIONED(bits) DUAL_XOR((bits), (bits) >> 2)
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#define CPU_FREQ F_CPU
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@ -47,22 +43,37 @@ inline static uint8_t sinSample(uint16_t i) {
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#define CONFIG_AFSK_TX_BUFLEN CONFIG_SAMPLERATE/150
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#define CONFIG_AFSK_RXTIMEOUT 0
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#define CONFIG_AFSK_TXWAIT 0UL
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#define CONFIG_AFSK_PREAMBLE_LEN 350UL
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#define CONFIG_AFSK_TRAILER_LEN 50UL
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#define CONFIG_AFSK_PREAMBLE_LEN 450UL
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#define CONFIG_AFSK_TRAILER_LEN 10UL
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#define BIT_STUFF_LEN 5
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#define BITRATE 1200
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#define SAMPLESPERBIT (CONFIG_SAMPLERATE / BITRATE)
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#define TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_SAMPLERATE) - 1)
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// TODO: Calculate based on sample rate [Done?]
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#define PHASE_BITS 8 // 8 // Sub-sample phase counter resolution
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#define PHASE_INC 1 // 1 // Nudge by above resolution for each adjustment
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// TODO: Maybe revert to only looking at two samples
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#if BITRATE == 1200
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#define SIGNAL_TRANSITIONED(bits) QUAD_XOR((bits), (bits) >> 4)
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#elif BITRATE == 2400
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#define SIGNAL_TRANSITIONED(bits) DUAL_XOR((bits), (bits) >> 2)
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#endif
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// TODO: Calculate based on sample rate [Done?]
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#define PHASE_BITS 8 // Sub-sample phase counter resolution
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#define PHASE_INC 1 // Nudge by above resolution for each adjustment
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#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS) // Size of our phase counter
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#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS) // 128 // Size of our phase counter
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// TODO: Test which target is best in real world
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#define PHASE_THRESHOLD (PHASE_MAX / 2)+3*PHASE_BITS // Target transition point of our phase window
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//#define PHASE_THRESHOLD (PHASE_MAX / 2) // 64 // Target transition point of our phase window
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// For 1200, this seems a little better
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#if BITRATE == 1200
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#define PHASE_THRESHOLD (PHASE_MAX / 2)+3*PHASE_BITS // Target transition point of our phase window
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//#define PHASE_THRESHOLD (PHASE_MAX / 2) // 64 // Target transition point of our phase window
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#elif BITRATE == 2400
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#define PHASE_THRESHOLD (PHASE_MAX / 2)+14 // Target transition point of our phase window
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#endif
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#define DCD_TIMEOUT_SAMPLES CONFIG_SAMPLERATE/100
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#define DCD_MIN_COUNT CONFIG_SAMPLERATE/1600
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@ -72,6 +83,16 @@ inline static uint8_t sinSample(uint16_t i) {
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#define FILTER_CUTOFF 600
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#define MARK_FREQ 1200
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#define SPACE_FREQ 2200
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#elif BITRATE == 2400
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#define FILTER_CUTOFF 772
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// #define MARK_FREQ 2165
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// #define SPACE_FREQ 3970
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#define MARK_FREQ 2200
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#define SPACE_FREQ 4000
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#elif BITRATE == 300
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#define FILTER_CUTOFF 600
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#define MARK_FREQ 1600
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#define SPACE_FREQ 1800
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#else
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#error Unsupported bitrate!
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#endif
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@ -117,7 +138,12 @@ typedef struct Afsk
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// Demodulation values
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FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination
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int8_t delayBuf[SAMPLESPERBIT / 2 + 1]; // Actual data storage for said FIFO
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#if BITRATE == 1200
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int8_t delayBuf[SAMPLESPERBIT / 2 + 1]; // Actual data storage for said FIFO
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//int8_t delayBuf[3 + 1]; // Actual data storage for said FIFO
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#elif BITRATE == 2400
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int8_t delayBuf[7 + 1]; // Actual data storage for said FIFO
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#endif
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FIFOBuffer rxFifo; // FIFO for received data
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uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
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@ -128,7 +154,9 @@ typedef struct Afsk
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#if SAMPLESPERBIT < 17
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uint16_t sampledBits; // Bits sampled by the demodulator (at ADC speed)
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#else
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#error Not enough space in sampledBits variable!
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// TODO: Enable error and set up correct size buffers
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uint16_t sampledBits;
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//#error Not enough space in sampledBits variable!
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#endif
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int16_t currentPhase; // Current phase of the demodulator
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uint8_t actualBits; // Actual found bits at correct bitrate
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@ -27,7 +27,12 @@ void kiss_init(AX25Ctx *ax25, Afsk *afsk, Serial *ser) {
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FLOWCONTROL = false;
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}
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// TODO: Revert to actual data
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size_t decodes = 0;
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void kiss_messageCallback(AX25Ctx *ctx) {
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decodes++;
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printf("%d\r\n", decodes);
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/*
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fputc(FEND, &serial->uart0);
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fputc(0x00, &serial->uart0);
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for (unsigned i = 0; i < ctx->frame_len-2; i++) {
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@ -42,7 +47,7 @@ void kiss_messageCallback(AX25Ctx *ctx) {
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fputc(b, &serial->uart0);
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}
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}
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fputc(FEND, &serial->uart0);
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fputc(FEND, &serial->uart0);*/
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}
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void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
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