Stuff not working
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@ -11,7 +11,7 @@
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#define CONFIG_AFSK_RXTIMEOUT 0 // How long a read operation from the modem
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// will wait for data before timing out.
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#define CONFIG_AFSK_PREAMBLE_LEN 250UL // The length of the packet preamble in milliseconds
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#define CONFIG_AFSK_PREAMBLE_LEN 500UL // The length of the packet preamble in milliseconds
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#define CONFIG_AFSK_TRAILER_LEN 100UL // The length of the packet tail in milliseconds
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#endif
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@ -4,7 +4,7 @@
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//////////////////////////////////////////////////////
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#include <cpu/irq.h> // Interrupt functionality from BertOS
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#include <cfg/debug.h> // Debug configuration from BertOS
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#include "cfg/debug.h" // Debug configuration from BertOS
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#include <drv/ser.h> // Serial driver from BertOS
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#include <drv/timer.h> // Timer driver from BertOS
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@ -101,6 +101,7 @@ int main(void)
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// and the byte is not a "transmit" (newline) character,
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// we should store it for transmission.
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if ((serialLen < MP1_MAX_FRAME_LENGTH) && (sbyte != 138)) {
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kprintf("%d\n", sbyte);
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// Put the read byte into the buffer;
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serialBuffer[serialLen] = sbyte;
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// Increment the read length counter
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@ -45,8 +45,8 @@ void mp1Poll(MP1 *mp1) {
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} else {
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// Checksum was incorrect
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//mp1Decode(mp1);
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//kprintf("Incorrect checksum. Found %d.\n", mp1->buffer[mp1->packetLength]);
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//kprintf("should be %d", mp1->checksum_in);
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kprintf("Incorrect checksum. Found %d, ", mp1->buffer[mp1->packetLength]);
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kprintf("should be %d\n", mp1->checksum_in);
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}
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}
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// If the above is not the case, this must be the
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@ -49,7 +49,7 @@
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* Baudrate for the debug console.
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* $WIZ$ type = "int"; min = 300
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*/
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#define CONFIG_KDEBUG_BAUDRATE 115200UL
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#define CONFIG_KDEBUG_BAUDRATE 57600UL
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/**
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* Clock source for the UART module. You need to write the code to reprogram the respective clock at the required frequency in your project before calling kdbg_init().
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@ -1,2 +1,2 @@
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#define VERS_BUILD 387
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#define VERS_BUILD 402
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#define VERS_HOST "vixen"
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