Migrated hardware
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@ -8,33 +8,32 @@
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#include <avr/interrupt.h>
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static Afsk *ctx;
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static Afsk *context;
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void hw_afsk_adcInit(int ch, Afsk *_ctx)
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void hw_afsk_adcInit(int ch, Afsk *_context)
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{
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ctx = _ctx;
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context = _context;
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ASSERT(ch <= 5);
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AFSK_STROBE_INIT();
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AFSK_STROBE_OFF();
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/* Set prescaler to clk/8 (2 MHz), CTC, top = ICR1 */
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// Timer/Counter Control Register 1 (Timer1 settings, for short)
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// Set prescaler to clk/8 (2 MHz), CTC, top = ICR1
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TCCR1A = 0;
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TCCR1B = BV(CS11) | BV(WGM13) | BV(WGM12);
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/* Set max value to obtain a 9600Hz freq */
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ICR1 = ((CPU_FREQ / 8) / 9600) - 1;
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// Configure ICR1 to get 9.6KHz sampling rate
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ICR1 = ((CPU_FREQ / 8) / 9600) - 1; // Input capture register
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/* Set reference to AVCC (5V), select CH */
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// Set reference to AVCC (5V), select pin
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ADMUX = BV(REFS0) | ch;
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DDRC &= ~BV(ch);
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PORTC &= ~BV(ch);
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DIDR0 |= BV(ch);
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/* Set autotrigger on Timer1 Input capture flag */
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ADCSRB = BV(ADTS2) | BV(ADTS1) | BV(ADTS0);
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/* Enable ADC, autotrigger, 1MHz, IRQ enabled */
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/* We are using the ADC a bit out of specifications otherwise it's not fast enough for our
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* purposes */
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// Set autotrigger on Timer1 Input capture flag
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ADCSRB = BV(ADTS2) | // Setting these three on (1-1-1) sets the ADC to
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BV(ADTS1) | // "Timer1 capture event"
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BV(ADTS0); //
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ADCSRA = BV(ADEN) | // ADC Enable
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BV(ADSC) | // ADC Start converting
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BV(ADATE) | // Enable autotriggering
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@ -43,17 +42,13 @@ void hw_afsk_adcInit(int ch, Afsk *_ctx)
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}
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// Declare ADC ISR
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bool hw_afsk_dac_isr;
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/*
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* This is how you declare an ISR.
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*/
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DECLARE_ISR(ADC_vect)
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{
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DECLARE_ISR(ADC_vect) {
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TIFR1 = BV(ICF1);
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afsk_adc_isr(ctx, ((int16_t)((ADC) >> 2) - 128));
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afsk_adc_isr(context, ((int16_t)((ADC) >> 2) - 128));
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if (hw_afsk_dac_isr)
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PORTD = afsk_dac_isr(ctx) & 0xF0;
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PORTD = afsk_dac_isr(context) & 0xF0;
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else
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PORTD = 128;
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}
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}
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@ -1,2 +1,2 @@
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#define VERS_BUILD 93
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#define VERS_BUILD 96
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#define VERS_HOST "vixen"
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