Work on sample rate independency
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3fb4c30604
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4
device.h
4
device.h
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@ -14,6 +14,7 @@
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// Sampling & timer setup
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#define CONFIG_SAMPLERATE 19200UL
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//#define CONFIG_SAMPLERATE 19200UL
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//#define CONFIG_SAMPLERATE 9600
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// Serial settings
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@ -21,6 +22,9 @@
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#define SERIAL_DEBUG false
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#define TX_MAXWAIT 2UL
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// CSMA Settings
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#define CONFIG_CSMA_P 255
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// Port settings
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#if TARGET_CPU == m1284p
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#define ADC_PORT PORTA
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@ -256,7 +256,7 @@ static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo) {
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// In this comparison we also detect when no transmission
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// (or silence) is taking place, and the demodulator
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// returns an endless stream of zeroes. Due to the NRZ-S
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// coding, the actual bits send to this function will
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// coding, the actual bits sent to this function will
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// be an endless stream of ones, which this AND operation
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// will also detect.
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if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET) {
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@ -549,13 +549,18 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
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ISR(ADC_vect) {
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TIFR1 = _BV(ICF1);
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//DAC_PORT ^= 0xFF;
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//DAC_PORT = ADCH;
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AFSK_adc_isr(AFSK_modem, (ADCH - 128));
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if (hw_afsk_dac_isr) {
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DAC_PORT = AFSK_dac_isr(AFSK_modem);
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LED_TX_ON();
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} else {
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DAC_PORT = 128;
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DAC_PORT = 127;
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LED_TX_OFF();
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}
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++_clock;
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@ -39,8 +39,8 @@ inline static uint8_t sinSample(uint16_t i) {
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#define CPU_FREQ F_CPU
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#define CONFIG_AFSK_RX_BUFLEN 64
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#define CONFIG_AFSK_TX_BUFLEN 64
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#define CONFIG_AFSK_RX_BUFLEN CONFIG_SAMPLERATE/150
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#define CONFIG_AFSK_TX_BUFLEN CONFIG_SAMPLERATE/150
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#define CONFIG_AFSK_RXTIMEOUT 0
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#define CONFIG_AFSK_TXWAIT 0UL
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#define CONFIG_AFSK_PREAMBLE_LEN 350UL
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@ -50,33 +50,25 @@ inline static uint8_t sinSample(uint16_t i) {
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#define BITRATE 1200
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#define SAMPLESPERBIT (CONFIG_SAMPLERATE / BITRATE)
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#define TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_SAMPLERATE) - 1)
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#define PHASE_INC 1 // Nudge by an eigth of a sample each adjustment
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#define DCD_MIN_COUNT 6
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#define DCD_TIMEOUT_SAMPLES 96
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#if BITRATE == 960
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#define FILTER_CUTOFF 600
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#define MARK_FREQ 960
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#define SPACE_FREQ 1600
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#define PHASE_BITS 10 // How much to increment phase counter each sample
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#elif BITRATE == 1200
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#define FILTER_CUTOFF 600
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#define MARK_FREQ 1200
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#define SPACE_FREQ 2200
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#define PHASE_BITS 8
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#elif BITRATE == 1600
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#define FILTER_CUTOFF 800
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#define MARK_FREQ 1600
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#define SPACE_FREQ 2600
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#define PHASE_BITS 8
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#else
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#error Unsupported bitrate!
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#endif
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// TODO: Calculate based on sample rate
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#define PHASE_INC SAMPLESPERBIT/8 // Nudge by an eigth of a sample each adjustment
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#define PHASE_BITS 8 // How much to increment phase counter each sample
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#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS) // Resolution of our phase counter = 64
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#define PHASE_THRESHOLD (PHASE_MAX / 2) // Target transition point of our phase window
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#define DCD_TIMEOUT_SAMPLES CONFIG_SAMPLERATE/100
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#define DCD_MIN_COUNT CONFIG_SAMPLERATE/1600
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#if BITRATE == 1200
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#define FILTER_CUTOFF 600
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#define MARK_FREQ 1200
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#define SPACE_FREQ 2200
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#else
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#error Unsupported bitrate!
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#endif
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typedef struct Hdlc
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{
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uint8_t demodulatedBits;
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@ -146,7 +138,7 @@ typedef struct Afsk
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#define AFSK_DAC_INIT() do { DAC_DDR |= 0xFF; } while (0)
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// Here's some macros for controlling the RX/TX LEDs
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// THE _INIT() functions writes to the DDRB register
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// THE _INIT() functions writes to the DDR registers
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// to configure the pins as output pins, and the _ON()
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// and _OFF() functions writes to the PORT registers
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// to turn the pins on or off.
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@ -18,7 +18,7 @@ unsigned long custom_preamble = CONFIG_AFSK_PREAMBLE_LEN;
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unsigned long custom_tail = CONFIG_AFSK_TRAILER_LEN;
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unsigned long slotTime = 200;
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uint8_t p = 63;
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uint8_t p = CONFIG_CSMA_P;
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void kiss_init(AX25Ctx *ax25, Afsk *afsk, Serial *ser) {
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ax25ctx = ax25;
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@ -55,7 +55,6 @@ void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
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}
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}
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while (!sent) {
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//puts("Waiting in CSMA");
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if(!channel->hdlc.dcd) {
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uint8_t tp = rand() & 0xFF;
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if (tp < p) {
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