Work on sample rate independency

This commit is contained in:
Mark Qvist 2018-12-29 15:57:49 +01:00
parent 3fb4c30604
commit f285ae8cc0
4 changed files with 30 additions and 30 deletions

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@ -14,6 +14,7 @@
// Sampling & timer setup
#define CONFIG_SAMPLERATE 19200UL
//#define CONFIG_SAMPLERATE 19200UL
//#define CONFIG_SAMPLERATE 9600
// Serial settings
@ -21,6 +22,9 @@
#define SERIAL_DEBUG false
#define TX_MAXWAIT 2UL
// CSMA Settings
#define CONFIG_CSMA_P 255
// Port settings
#if TARGET_CPU == m1284p
#define ADC_PORT PORTA

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@ -256,7 +256,7 @@ static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo) {
// In this comparison we also detect when no transmission
// (or silence) is taking place, and the demodulator
// returns an endless stream of zeroes. Due to the NRZ-S
// coding, the actual bits send to this function will
// coding, the actual bits sent to this function will
// be an endless stream of ones, which this AND operation
// will also detect.
if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET) {
@ -549,13 +549,18 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
ISR(ADC_vect) {
TIFR1 = _BV(ICF1);
//DAC_PORT ^= 0xFF;
//DAC_PORT = ADCH;
AFSK_adc_isr(AFSK_modem, (ADCH - 128));
if (hw_afsk_dac_isr) {
DAC_PORT = AFSK_dac_isr(AFSK_modem);
LED_TX_ON();
} else {
DAC_PORT = 128;
DAC_PORT = 127;
LED_TX_OFF();
}
++_clock;

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@ -39,8 +39,8 @@ inline static uint8_t sinSample(uint16_t i) {
#define CPU_FREQ F_CPU
#define CONFIG_AFSK_RX_BUFLEN 64
#define CONFIG_AFSK_TX_BUFLEN 64
#define CONFIG_AFSK_RX_BUFLEN CONFIG_SAMPLERATE/150
#define CONFIG_AFSK_TX_BUFLEN CONFIG_SAMPLERATE/150
#define CONFIG_AFSK_RXTIMEOUT 0
#define CONFIG_AFSK_TXWAIT 0UL
#define CONFIG_AFSK_PREAMBLE_LEN 350UL
@ -50,33 +50,25 @@ inline static uint8_t sinSample(uint16_t i) {
#define BITRATE 1200
#define SAMPLESPERBIT (CONFIG_SAMPLERATE / BITRATE)
#define TICKS_BETWEEN_SAMPLES ((((CPU_FREQ+FREQUENCY_CORRECTION)) / CONFIG_SAMPLERATE) - 1)
#define PHASE_INC 1 // Nudge by an eigth of a sample each adjustment
#define DCD_MIN_COUNT 6
#define DCD_TIMEOUT_SAMPLES 96
#if BITRATE == 960
#define FILTER_CUTOFF 600
#define MARK_FREQ 960
#define SPACE_FREQ 1600
#define PHASE_BITS 10 // How much to increment phase counter each sample
#elif BITRATE == 1200
#define FILTER_CUTOFF 600
#define MARK_FREQ 1200
#define SPACE_FREQ 2200
#define PHASE_BITS 8
#elif BITRATE == 1600
#define FILTER_CUTOFF 800
#define MARK_FREQ 1600
#define SPACE_FREQ 2600
#define PHASE_BITS 8
#else
#error Unsupported bitrate!
#endif
// TODO: Calculate based on sample rate
#define PHASE_INC SAMPLESPERBIT/8 // Nudge by an eigth of a sample each adjustment
#define PHASE_BITS 8 // How much to increment phase counter each sample
#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS) // Resolution of our phase counter = 64
#define PHASE_THRESHOLD (PHASE_MAX / 2) // Target transition point of our phase window
#define DCD_TIMEOUT_SAMPLES CONFIG_SAMPLERATE/100
#define DCD_MIN_COUNT CONFIG_SAMPLERATE/1600
#if BITRATE == 1200
#define FILTER_CUTOFF 600
#define MARK_FREQ 1200
#define SPACE_FREQ 2200
#else
#error Unsupported bitrate!
#endif
typedef struct Hdlc
{
uint8_t demodulatedBits;
@ -146,7 +138,7 @@ typedef struct Afsk
#define AFSK_DAC_INIT() do { DAC_DDR |= 0xFF; } while (0)
// Here's some macros for controlling the RX/TX LEDs
// THE _INIT() functions writes to the DDRB register
// THE _INIT() functions writes to the DDR registers
// to configure the pins as output pins, and the _ON()
// and _OFF() functions writes to the PORT registers
// to turn the pins on or off.

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@ -18,7 +18,7 @@ unsigned long custom_preamble = CONFIG_AFSK_PREAMBLE_LEN;
unsigned long custom_tail = CONFIG_AFSK_TRAILER_LEN;
unsigned long slotTime = 200;
uint8_t p = 63;
uint8_t p = CONFIG_CSMA_P;
void kiss_init(AX25Ctx *ax25, Afsk *afsk, Serial *ser) {
ax25ctx = ax25;
@ -55,7 +55,6 @@ void kiss_csma(AX25Ctx *ctx, uint8_t *buf, size_t len) {
}
}
while (!sent) {
//puts("Waiting in CSMA");
if(!channel->hdlc.dcd) {
uint8_t tp = rand() & 0xFF;
if (tp < p) {