150 lines
3.5 KiB
C
150 lines
3.5 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2008 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief Configuration file for the ADC module.
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*
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* \author Daniele Basile <asterix@develer.com>
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*/
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#ifndef CFG_ADC_H
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#define CFG_ADC_H
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/**
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* Module logging level.
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*
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* $WIZ$ type = "enum"
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* $WIZ$ value_list = "log_level"
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*/
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#define ADC_LOG_LEVEL LOG_LVL_INFO
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/**
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* Module logging format.
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*
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* $WIZ$ type = "enum"
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* $WIZ$ value_list = "log_format"
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*/
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#define ADC_LOG_FORMAT LOG_FMT_VERBOSE
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/**
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* Clock Frequency for ADC conversion.
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* This frequency will be rounded down to an integer
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* submultiple of CPU_FREQ.
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*
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* $WIZ$ type = "int"
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* $WIZ$ supports = "at91"
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* $WIZ$ max = 5000000
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*/
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#define CONFIG_ADC_CLOCK 4800000UL
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/**
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* Minimum time for starting up a conversion [us].
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*
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* $WIZ$ type = "int"
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* $WIZ$ min = 20
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* $WIZ$ supports = "at91"
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*/
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#define CONFIG_ADC_STARTUP_TIME 20
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/**
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* Minimum time for sample and hold [ns].
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*
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* $WIZ$ type = "int"
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* $WIZ$ min = 600
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* $WIZ$ supports = "at91"
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*/
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#define CONFIG_ADC_SHTIME 834
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/**
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* ADC Voltage Reference.
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*
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* $WIZ$ type = "enum"
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* $WIZ$ value_list = "avr_adc_refs"
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* $WIZ$ supports = "avr"
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*/
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#define CONFIG_ADC_AVR_REF ADC_AVR_AVCC
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/**
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* ADC clock divisor from main crystal.
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*
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* $WIZ$ type = "int"
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* $WIZ$ min = 2
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* $WIZ$ max = 128
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* $WIZ$ supports = "avr"
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*/
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#define CONFIG_ADC_AVR_DIVISOR 2
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/**
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* Enable ADC strobe for debugging ADC ISR.
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*
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* $WIZ$ type = "boolean"
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*/
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#define CONFIG_ADC_STROBE 0
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/**
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* Start up timer[s] = startup value / ADCClock [Hz]
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*
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* $WIZ$ type = "enum"
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* $WIZ$ value_list = "sam3_adc_sut"
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* $WIZ$ supports = "sam3"
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*/
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#define CONFIG_ADC_SUT ADC_SUT512
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/**
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* Analog Settling Time[s] = settling value / ADCClock[Hz]
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*
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* $WIZ$ type = "enum"
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* $WIZ$ value_list = "sam3_adc_stt"
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* $WIZ$ supports = "sam3"
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*/
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#define CONFIG_ADC_STTLING ADC_AST17
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/**
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* Tracking Time[s] = (TRACKTIM + 1) / ADCClock[Hz]
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*
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* $WIZ$ type = "int"
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* $WIZ$ min = 0
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* $WIZ$ supports = "sam3"
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*/
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#define CONFIG_ADC_TRACKTIM 0
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/**
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* Transfer Period[s] = (TRANSFER * 2 + 3) ADCClock[Hz]
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*
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* $WIZ$ type = "int"
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* $WIZ$ min = 0
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* $WIZ$ supports = "sam3"
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*/
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#define CONFIG_ADC_TRANSFER 1
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#endif /* CFG_ADC_H */
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