18 lines
271 B
VHDL
18 lines
271 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity test is
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port(
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clk : in std_logic;
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d : in std_logic ;
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q :out std_logic );
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end test;
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architecture rtl of test is
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begin
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process (clk)
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begin
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if rising_edge(clk) then
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q <= d;
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end if;
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end;
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end rtl;
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