34 lines
630 B
Coq
34 lines
630 B
Coq
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// Testbench
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module test;
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reg clk;
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reg reset;
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reg d;
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wire q;
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wire qb;
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// Instantiate design under test
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dff DFF(.clk(clk), .reset(reset),
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.d(d), .q(q), .qb(qb));
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initial begin
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// Dump waves
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$dumpfile("dump.vcd");
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$dumpvars(1);
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$display("Reset flop.");
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clk = 0;
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reset = 1;
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d = 1'bx;
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display;
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$display("Release reset.");
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d = 1;
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reset = 0;
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display;
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$display("Toggle clk.");
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clk = 1;
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display;
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end
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task display;
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#1 $display("d:%0h, q:%0h, qb:%0h",
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d, q, qb);
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endtask
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endmodule
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