diff --git a/examples/nested-jsbeautifyrc/verilog/expected/test.v b/examples/nested-jsbeautifyrc/verilog/expected/test.v
index 6dd5d4d..5e2198c 100644
--- a/examples/nested-jsbeautifyrc/verilog/expected/test.v
+++ b/examples/nested-jsbeautifyrc/verilog/expected/test.v
@@ -1,33 +1,33 @@
 // Testbench
 module test;
-   reg clk;
-   reg reset;
-   reg d;
-   wire q;
-   wire qb;
-   // Instantiate design under test
-   dff DFF(.clk(clk), .reset(reset),
-           .d(d), .q(q), .qb(qb));
+  reg clk;
+  reg reset;
+  reg d;
+  wire q;
+  wire qb;
+  // Instantiate design under test
+  dff DFF(.clk(clk), .reset(reset),
+          .d(d), .q(q), .qb(qb));
 
-   initial begin
-      // Dump waves
-      $dumpfile("dump.vcd");
-      $dumpvars(1);
-      $display("Reset flop.");
-      clk = 0;
-      reset = 1;
-      d = 1'bx;
-      display;
-      $display("Release reset.");
-      d = 1;
-      reset = 0;
-      display;
-      $display("Toggle clk.");
-      clk = 1;
-      display;
-   end
-   task display;
-      #1 $display("d:%0h, q:%0h, qb:%0h",
-                  d, q, qb);
-   endtask
+  initial begin
+    // Dump waves
+    $dumpfile("dump.vcd");
+    $dumpvars(1);
+    $display("Reset flop.");
+    clk = 0;
+    reset = 1;
+    d = 1'bx;
+    display;
+    $display("Release reset.");
+    d = 1;
+    reset = 0;
+    display;
+    $display("Toggle clk.");
+    clk = 1;
+    display;
+  end
+  task display;
+    #1 $display("d:%0h, q:%0h, qb:%0h",
+                d, q, qb);
+  endtask
 endmodule
diff --git a/src/beautifiers/verilog-mode/verilog-mode.el b/src/beautifiers/verilog-mode/verilog-mode.el
index 74132cb..968338c 100644
--- a/src/beautifiers/verilog-mode/verilog-mode.el
+++ b/src/beautifiers/verilog-mode/verilog-mode.el
@@ -1,3 +1,22 @@
 (add-hook 'verilog-mode-hook '(lambda ()
     (add-hook 'local-write-file-hooks (lambda()
        (untabify (point-min) (point-max))))))
+
+(custom-set-variables
+ '(verilog-align-ifelse t)
+ '(verilog-auto-delete-trailing-whitespace t)
+ '(verilog-auto-inst-param-value t)
+ '(verilog-auto-inst-vector nil)
+ '(verilog-auto-lineup (quote all))
+ '(verilog-auto-newline nil)
+ '(verilog-auto-save-policy nil)
+ '(verilog-auto-template-warn-unused t)
+ '(verilog-case-indent 2)
+ '(verilog-cexp-indent 2)
+ '(verilog-highlight-grouping-keywords t)
+ '(verilog-highlight-modules t)
+ '(verilog-indent-level 2)
+ '(verilog-indent-level-behavioral 2)
+ '(verilog-indent-level-declaration 2)
+ '(verilog-indent-level-module 2)
+ '(verilog-tab-to-comment t))