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3 Commits

Author SHA1 Message Date
Steven Zeck 4cd81a388d
Disable gn and verilog CI tests for now 2018-03-02 11:53:38 -06:00
Andrew Andrianov 5bcb09d340 verilog: Add more options for verilog-mode.el 
Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
 2018-02-12 16:09:25 +03:00
Andrew Andrianov 6db872294e beautifiers: Add support for Verilog/SystemVerilog beautification 
Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
 2018-02-07 13:15:21 +03:00