270 lines
8.8 KiB
Plaintext
270 lines
8.8 KiB
Plaintext
#include "marlin.cuh"
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800
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namespace marlin {
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template <int const num_threads, int const num_bits, bool const has_perm>
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__global__ void awq_marlin_repack_kernel(
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uint32_t const* __restrict__ b_q_weight_ptr, uint32_t* __restrict__ out_ptr,
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int size_k, int size_n) {}
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} // namespace marlin
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torch::Tensor awq_marlin_repack(torch::Tensor& b_q_weight, torch::Tensor& perm,
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int64_t size_k, int64_t size_n,
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int64_t num_bits) {
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TORCH_CHECK_NOT_IMPLEMENTED(
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false, "marlin_repack_from_gptq(..) requires CUDA_ARCH >= 8.0");
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return torch::empty({1, 1});
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}
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#else
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namespace marlin {
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template <int const num_threads, int const num_bits>
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__global__ void awq_marlin_repack_kernel(
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uint32_t const* __restrict__ b_q_weight_ptr, uint32_t* __restrict__ out_ptr,
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int size_k, int size_n) {
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constexpr int pack_factor = 32 / num_bits;
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int k_tiles = size_k / tile_k_size;
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int n_tiles = size_n / tile_n_size;
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int block_k_tiles = div_ceil(k_tiles, gridDim.x);
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int start_k_tile = blockIdx.x * block_k_tiles;
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if (start_k_tile >= k_tiles) {
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return;
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}
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int finish_k_tile = min(start_k_tile + block_k_tiles, k_tiles);
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// Wait until the next thread tile has been loaded to shared memory.
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auto wait_for_stage = [&]() {
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// We only have `stages - 2` active fetches since we are double buffering
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// and can only issue the next fetch when it is guaranteed that the previous
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// shared memory load is fully complete (as it may otherwise be
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// overwritten).
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cp_async_wait<repack_stages - 2>();
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__syncthreads();
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};
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extern __shared__ int4 sh[];
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constexpr int tile_n_ints = tile_n_size / pack_factor;
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constexpr int stage_n_threads = tile_n_ints / 4;
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constexpr int stage_k_threads = tile_k_size;
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constexpr int stage_size = stage_k_threads * stage_n_threads;
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auto fetch_to_shared = [&](int pipe, int k_tile_id, int n_tile_id) {
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if (n_tile_id >= n_tiles) {
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cp_async_fence();
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return;
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}
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int first_n = n_tile_id * tile_n_size;
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int first_n_packed = first_n / pack_factor;
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int4* sh_ptr = sh + stage_size * pipe;
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if (threadIdx.x < stage_size) {
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int k_id = threadIdx.x / stage_n_threads;
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int n_id = threadIdx.x % stage_n_threads;
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int first_k = k_tile_id * tile_k_size;
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cp_async4(&sh_ptr[k_id * stage_n_threads + n_id],
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reinterpret_cast<int4 const*>(
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&(b_q_weight_ptr[(first_k + k_id) * (size_n / pack_factor) +
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first_n_packed + (n_id * 4)])));
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}
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cp_async_fence();
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};
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auto repack_tile = [&](int pipe, int k_tile_id, int n_tile_id) {
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if (n_tile_id >= n_tiles) {
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return;
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}
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int warp_id = threadIdx.x / 32;
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int th_id = threadIdx.x % 32;
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if (warp_id >= 4) {
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return;
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}
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int tc_col = th_id / 4;
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int tc_row = (th_id % 4) * 2;
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constexpr int tc_offsets[4] = {0, 1, 8, 9};
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int cur_n = warp_id * 16 + tc_col;
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int cur_n_packed = cur_n / pack_factor;
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int cur_n_pos = cur_n % pack_factor;
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constexpr int sh_stride = tile_n_ints;
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constexpr uint32_t mask = (1 << num_bits) - 1;
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int4* sh_stage_ptr = sh + stage_size * pipe;
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uint32_t* sh_stage_int_ptr = reinterpret_cast<uint32_t*>(sh_stage_ptr);
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// Undo interleaving
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int cur_n_pos_unpacked;
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if constexpr (num_bits == 4) {
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constexpr int undo_pack[8] = {0, 4, 1, 5, 2, 6, 3, 7};
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cur_n_pos_unpacked = undo_pack[cur_n_pos];
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} else {
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constexpr int undo_pack[4] = {0, 2, 1, 3};
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cur_n_pos_unpacked = undo_pack[cur_n_pos];
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}
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uint32_t vals[8];
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#pragma unroll
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for (int i = 0; i < 4; i++) {
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int cur_elem = tc_row + tc_offsets[i];
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int packed_src_0 = sh_stage_int_ptr[cur_n_packed + sh_stride * cur_elem];
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int packed_src_1 = sh_stage_int_ptr[cur_n_packed + (8 / pack_factor) +
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sh_stride * cur_elem];
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vals[i] = (packed_src_0 >> (cur_n_pos_unpacked * num_bits)) & mask;
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vals[4 + i] = (packed_src_1 >> (cur_n_pos_unpacked * num_bits)) & mask;
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}
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constexpr int tile_size = tile_k_size * tile_n_size / pack_factor;
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int out_offset = (k_tile_id * n_tiles + n_tile_id) * tile_size;
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// Result of:
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// https://github.com/NVIDIA/FasterTransformer/blob/main/src/fastertransformer/cutlass_extensions/include/cutlass_extensions/interleaved_numeric_conversion.h
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if constexpr (num_bits == 4) {
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constexpr int pack_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
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uint32_t res = 0;
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#pragma unroll
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for (int i = 0; i < 8; i++) {
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res |= vals[pack_idx[i]] << (i * 4);
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}
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out_ptr[out_offset + th_id * 4 + warp_id] = res;
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} else {
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constexpr int pack_idx[4] = {0, 2, 1, 3};
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uint32_t res1 = 0;
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uint32_t res2 = 0;
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#pragma unroll
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for (int i = 0; i < 4; i++) {
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res1 |= vals[pack_idx[i]] << (i * 8);
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res2 |= vals[4 + pack_idx[i]] << (i * 8);
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}
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out_ptr[out_offset + th_id * 8 + (warp_id * 2) + 0] = res1;
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out_ptr[out_offset + th_id * 8 + (warp_id * 2) + 1] = res2;
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}
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};
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auto start_pipes = [&](int k_tile_id, int n_tile_id) {
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#pragma unroll
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for (int pipe = 0; pipe < repack_stages - 1; pipe++) {
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fetch_to_shared(pipe, k_tile_id, n_tile_id + pipe);
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}
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wait_for_stage();
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};
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#pragma unroll
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for (int k_tile_id = start_k_tile; k_tile_id < finish_k_tile; k_tile_id++) {
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int n_tile_id = 0;
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start_pipes(k_tile_id, n_tile_id);
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while (n_tile_id < n_tiles) {
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#pragma unroll
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for (int pipe = 0; pipe < repack_stages; pipe++) {
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fetch_to_shared((pipe + repack_stages - 1) % repack_stages, k_tile_id,
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n_tile_id + pipe + repack_stages - 1);
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repack_tile(pipe, k_tile_id, n_tile_id + pipe);
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wait_for_stage();
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}
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n_tile_id += repack_stages;
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}
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}
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}
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} // namespace marlin
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#define CALL_IF(NUM_BITS) \
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else if (num_bits == NUM_BITS) { \
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cudaFuncSetAttribute( \
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marlin::awq_marlin_repack_kernel<marlin::repack_threads, NUM_BITS>, \
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cudaFuncAttributeMaxDynamicSharedMemorySize, max_shared_mem); \
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marlin::awq_marlin_repack_kernel<marlin::repack_threads, NUM_BITS> \
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<<<blocks, marlin::repack_threads, max_shared_mem, stream>>>( \
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b_q_weight_ptr, out_ptr, size_k, size_n); \
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}
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torch::Tensor awq_marlin_repack(torch::Tensor& b_q_weight, int64_t size_k,
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int64_t size_n, int64_t num_bits) {
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// Verify compatibility with marlin tile of 16x64
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TORCH_CHECK(size_k % marlin::tile_k_size == 0, "size_k = ", size_k,
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" is not divisible by tile_k_size = ", marlin::tile_k_size);
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TORCH_CHECK(size_n % marlin::tile_n_size == 0, "size_n = ", size_n,
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" is not divisible by tile_n_size = ", marlin::tile_n_size);
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TORCH_CHECK(num_bits == 4 || num_bits == 8,
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"num_bits must be 4 or 8. Got = ", num_bits);
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int const pack_factor = 32 / num_bits;
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// Verify B
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TORCH_CHECK(b_q_weight.size(0) == size_k,
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"b_q_weight.size(0) = ", b_q_weight.size(0),
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" is not size_k = ", size_k);
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TORCH_CHECK((size_n / pack_factor) == b_q_weight.size(1),
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"Shape mismatch: b_q_weight.size(1) = ", b_q_weight.size(1),
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", size_n = ", size_n, ", pack_factor = ", pack_factor);
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// Verify device and strides
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TORCH_CHECK(b_q_weight.device().is_cuda(), "b_q_weight is not on GPU");
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TORCH_CHECK(b_q_weight.is_contiguous(), "b_q_weight is not contiguous");
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TORCH_CHECK(b_q_weight.dtype() == at::kInt, "b_q_weight type is not kInt");
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// Alloc buffers
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const at::cuda::OptionalCUDAGuard device_guard(device_of(b_q_weight));
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auto options = torch::TensorOptions()
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.dtype(b_q_weight.dtype())
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.device(b_q_weight.device());
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torch::Tensor out = torch::empty(
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{size_k / marlin::tile_size, size_n * marlin::tile_size / pack_factor},
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options);
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// Get ptrs
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uint32_t const* b_q_weight_ptr =
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reinterpret_cast<uint32_t const*>(b_q_weight.data_ptr());
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uint32_t* out_ptr = reinterpret_cast<uint32_t*>(out.data_ptr());
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// Get dev info
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int dev = b_q_weight.get_device();
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cudaStream_t stream = at::cuda::getCurrentCUDAStream(dev);
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int blocks;
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cudaDeviceGetAttribute(&blocks, cudaDevAttrMultiProcessorCount, dev);
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int max_shared_mem = 0;
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cudaDeviceGetAttribute(&max_shared_mem,
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cudaDevAttrMaxSharedMemoryPerBlockOptin, dev);
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TORCH_CHECK(max_shared_mem > 0);
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if (false) {
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}
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CALL_IF(4)
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CALL_IF(8)
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else {
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TORCH_CHECK(false, "Unsupported repack config: num_bits = ", num_bits);
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}
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return out;
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}
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#endif
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