Merge pull request #606
8ce12a9
Fix arm asm (Howard Chu)94de39f
Tweak arm6 flags (Howard Chu)
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commit
92b753d5e4
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@ -284,7 +284,7 @@ if(MSVC)
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else()
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set(ARCH native CACHE STRING "CPU to build for: -march value or default")
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# -march=armv7-a conflicts with -mcpu=cortex-a7
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if(ARCH STREQUAL "default" OR ARM7)
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if(ARCH STREQUAL "default" OR ARM7 OR ARM6)
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set(ARCH_FLAG "")
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else()
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if(ARCH STREQUAL "x86_64")
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@ -663,31 +663,71 @@ static void (*const extra_hashes[4])(const void *, size_t, char *) = {
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#include "aesb.c"
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STATIC INLINE void ___mul128(uint32_t *a, uint32_t *b, uint32_t *h, uint32_t *l)
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{
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// ND: 64x64 multiplication for ARM7
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__asm__ __volatile__
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(
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// lo hi
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"umull %[r0], %[r1], %[b], %[d]\n\t" // bd [r0 = bd.lo]
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"umull %[r2], %[r3], %[b], %[c]\n\t" // bc
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"umull %[b], %[c], %[a], %[c]\n\t" // ac
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"adds %[r1], %[r1], %[r2]\n\t" // r1 = bd.hi + bc.lo
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"adcs %[r2], %[r3], %[b]\n\t" // r2 = ac.lo + bc.hi + carry
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"adc %[r3], %[c], #0\n\t" // r3 = ac.hi + carry
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"umull %[b], %[a], %[a], %[d]\n\t" // ad
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"adds %[r1], %[r1], %[b]\n\t" // r1 = bd.hi + bc.lo + ad.lo
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"adcs %[r2], %[r2], %[a]\n\t" // r2 = ac.lo + bc.hi + ad.hi + carry
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"adc %[r3], %[r3], #0\n\t" // r3 = ac.hi + carry
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: [r0]"=&r"(l[0]), [r1]"=&r"(l[1]), [r2]"=&r"(h[0]), [r3]"=&r"(h[1])
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: [a]"r"(a[1]), [b]"r"(a[0]), [c]"r"(b[1]), [d]"r"(b[0])
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: "cc"
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);
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}
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/* The asm corresponds to this C code
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#define SHORT uint32_t
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#define LONG uint64_t
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STATIC INLINE void mul(const uint8_t* a, const uint8_t* b, uint8_t* res)
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void mul(const uint8_t *ca, const uint8_t *cb, uint8_t *cres) {
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const SHORT *aa = (SHORT *)ca;
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const SHORT *bb = (SHORT *)cb;
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SHORT *res = (SHORT *)cres;
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union {
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SHORT tmp[8];
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LONG ltmp[4];
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} t;
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LONG A = aa[1];
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LONG a = aa[0];
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LONG B = bb[1];
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LONG b = bb[0];
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// Aa * Bb = ab + aB_ + Ab_ + AB__
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t.ltmp[0] = a * b;
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t.ltmp[1] = a * B;
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t.ltmp[2] = A * b;
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t.ltmp[3] = A * B;
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res[2] = t.tmp[0];
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t.ltmp[1] += t.tmp[1];
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t.ltmp[1] += t.tmp[4];
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t.ltmp[3] += t.tmp[3];
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t.ltmp[3] += t.tmp[5];
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res[3] = t.tmp[2];
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res[0] = t.tmp[6];
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res[1] = t.tmp[7];
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} */
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/* Can work as inline, but actually runs slower. Keep it separate */
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#define mul(a, b, c) cn_mul128(a, b, c)
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void mul(const uint8_t *ca, const uint8_t *cb, uint8_t *cr)
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{
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___mul128((uint32_t *) a, (uint32_t *) b, (uint32_t *) (res + 0), (uint32_t *) (res + 8));
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const uint32_t *aa = (uint32_t *)ca;
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const uint32_t *bb = (uint32_t *)cb;
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uint32_t *r = (uint32_t *)cr;
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uint32_t t0, t1;
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__asm__ __volatile__(
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"umull %[t0], %[t1], %[a], %[b]\n\t"
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"str %[t0], [%[r], #8]\n\t"
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// accumulating with 0 can never overflow/carry
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"mov %[t0], #0\n\t"
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"umlal %[t1], %[t0], %[a], %[B]\n\t"
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"mov %[a], #0\n\t"
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"umlal %[t1], %[a], %[A], %[b]\n\t"
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"str %[t1], [%[r], #12]\n\t"
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"mov %[b], #0\n\t"
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"umlal %[t0], %[b], %[A], %[B]\n\t"
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// final add may have a carry
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"adds %[t0], %[t0], %[a]\n\t"
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"adc %[t1], %[b], #0\n\t"
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"str %[t0], [%[r]]\n\t"
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"str %[t1], [%[r], #4]\n\t"
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: [t0]"=&r"(t0), [t1]"=&r"(t1)
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: [A]"r"(aa[1]), [a]"r"(aa[0]), [B]"r"(bb[1]), [b]"r"(bb[0]), [r]"r"(r)
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: "cc", "memory");
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}
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STATIC INLINE void sum_half_blocks(uint8_t* a, const uint8_t* b)
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