mod variant4_random_math
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@ -200,7 +200,6 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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memset(data, 0, sizeof(data));
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uint64_t tmp = SWAP64LE(height);
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memcpy(data, &tmp, sizeof(uint64_t));
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data[20] = -38; // change seed
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// Set data_index past the last byte in data
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// to trigger full data update with blake hash
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@ -211,10 +210,9 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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// There is a small chance (1.8%) that register R8 won't be used in the generated program
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// So we keep track of it and try again if it's not used
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bool r8_used;
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do {
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int latency[9];
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int asic_latency[9];
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int latency[8];
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int asic_latency[8];
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// Tracks previous instruction and value of the source operand for registers R0-R3 throughout code execution
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// byte 0: current value of the destination register
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@ -223,7 +221,7 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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//
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// Registers R4-R8 are constant and are treated as having the same value because when we do
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// the same operation twice with two constant source registers, it can be optimized into a single operation
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uint32_t inst_data[9] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
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uint32_t inst_data[8] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
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bool alu_busy[TOTAL_LATENCY + 1][ALU_COUNT];
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bool is_rotation[V4_INSTRUCTION_COUNT];
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@ -242,7 +240,6 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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code_size = 0;
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int total_iterations = 0;
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r8_used = false;
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// Generate random code to achieve minimal required latency for our abstract CPU
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// Try to get this latency for all 4 registers
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@ -287,8 +284,8 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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if (((opcode == ADD) || (opcode == SUB) || (opcode == XOR)) && (a == b))
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{
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// Use register R8 as source instead
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b = 8;
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src_index = 8;
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b = a + 4;
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src_index = b;
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}
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// Don't do rotation with the same destination twice because it's equal to a single rotation
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@ -368,10 +365,6 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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code[code_size].src_index = src_index;
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code[code_size].C = 0;
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if (src_index == 8)
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{
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r8_used = true;
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}
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if (opcode == ADD)
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{
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@ -402,7 +395,7 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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// We need to add a few more MUL and ROR instructions to achieve minimal required latency for ASIC
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// Get this latency for at least 1 of the 4 registers
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const int prev_code_size = code_size;
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while ((code_size < NUM_INSTRUCTIONS_MAX) && (asic_latency[0] < TOTAL_LATENCY) && (asic_latency[1] < TOTAL_LATENCY) && (asic_latency[2] < TOTAL_LATENCY) && (asic_latency[3] < TOTAL_LATENCY))
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while ((asic_latency[0] < TOTAL_LATENCY) && (asic_latency[1] < TOTAL_LATENCY) && (asic_latency[2] < TOTAL_LATENCY) && (asic_latency[3] < TOTAL_LATENCY))
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{
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int min_idx = 0;
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int max_idx = 0;
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@ -426,7 +419,7 @@ static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_
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// There is ~98.15% chance that loop condition is false, so this loop will execute only 1 iteration most of the time
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// It never does more than 4 iterations for all block heights < 10,000,000
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} while (!r8_used || (code_size < NUM_INSTRUCTIONS_MIN) || (code_size > NUM_INSTRUCTIONS_MAX));
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} while (code_size < NUM_INSTRUCTIONS_MIN);
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// It's guaranteed that NUM_INSTRUCTIONS_MIN <= code_size <= NUM_INSTRUCTIONS_MAX here
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// Add final instruction to stop the interpreter
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