263 lines
6.5 KiB
C
263 lines
6.5 KiB
C
/*
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This file contains a useful c translation of the datasheet register map values
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*/
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#ifndef _ICM_20948_ENUMERATIONS_H_
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#define _ICM_20948_ENUMERATIONS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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// // Generalized
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// REG_BANK_SEL = 0x7F,
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// // Gyroscope and Accelerometer
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// // User Bank 0
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// AGB0_REG_WHO_AM_I = 0x00,
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// // Break
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// AGB0_REG_USER_CTRL = 0x03,
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// // Break
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// AGB0_REG_LP_CONFIG = 0x05,
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typedef enum{
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ICM_20948_Sample_Mode_Continuous = 0x00,
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ICM_20948_Sample_Mode_Cycled,
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}ICM_20948_LP_CONFIG_CYCLE_e;
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// AGB0_REG_PWR_MGMT_1,
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typedef enum{
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ICM_20948_Clock_Internal_20MHz = 0x00,
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ICM_20948_Clock_Auto,
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ICM_20948_Clock_TimingReset = 0x07
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}ICM_20948_PWR_MGMT_1_CLKSEL_e;
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// AGB0_REG_PWR_MGMT_2,
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// // Break
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// AGB0_REG_INT_PIN_CONFIG = 0x0F,
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// AGB0_REG_INT_ENABLE,
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// AGB0_REG_INT_ENABLE_1,
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// AGB0_REG_INT_ENABLE_2,
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// AGB0_REG_INT_ENABLE_3,
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// // Break
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// AGB0_REG_I2C_MST_STATUS = 0x17,
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// // Break
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// AGB0_REG_INT_STATUS = 0x19,
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// AGB0_REG_INT_STATUS_1,
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// AGB0_REG_INT_STATUS_2,
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// AGB0_REG_INT_STATUS_3,
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// // Break
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// AGB0_REG_DELAY_TIMEH = 0x28,
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// AGB0_REG_DELAY_TIMEL,
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// // Break
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// AGB0_REG_ACCEL_XOUT_H = 0x2D,
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// AGB0_REG_ACCEL_XOUT_L,
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// AGB0_REG_ACCEL_YOUT_H,
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// AGB0_REG_ACCEL_YOUT_L,
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// AGB0_REG_ACCEL_ZOUT_H,
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// AGB0_REG_ACCEL_ZOUT_L,
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// AGB0_REG_GYRO_XOUT_H,
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// AGB0_REG_GYRO_XOUT_L,
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// AGB0_REG_GYRO_YOUT_H,
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// AGB0_REG_GYRO_YOUT_L,
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// AGB0_REG_GYRO_ZOUT_H,
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// AGB0_REG_GYRO_ZOUT_L,
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// AGB0_REG_TEMP_OUT_H,
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// AGB0_REG_TEMP_OUT_L,
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// AGB0_REG_EXT_SLV_SENS_DATA_00,
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// AGB0_REG_EXT_SLV_SENS_DATA_01,
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// AGB0_REG_EXT_SLV_SENS_DATA_02,
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// AGB0_REG_EXT_SLV_SENS_DATA_03,
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// AGB0_REG_EXT_SLV_SENS_DATA_04,
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// AGB0_REG_EXT_SLV_SENS_DATA_05,
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// AGB0_REG_EXT_SLV_SENS_DATA_06,
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// AGB0_REG_EXT_SLV_SENS_DATA_07,
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// AGB0_REG_EXT_SLV_SENS_DATA_08,
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// AGB0_REG_EXT_SLV_SENS_DATA_09,
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// AGB0_REG_EXT_SLV_SENS_DATA_10,
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// AGB0_REG_EXT_SLV_SENS_DATA_11,
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// AGB0_REG_EXT_SLV_SENS_DATA_12,
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// AGB0_REG_EXT_SLV_SENS_DATA_13,
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// AGB0_REG_EXT_SLV_SENS_DATA_14,
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// AGB0_REG_EXT_SLV_SENS_DATA_15,
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// AGB0_REG_EXT_SLV_SENS_DATA_16,
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// AGB0_REG_EXT_SLV_SENS_DATA_17,
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// AGB0_REG_EXT_SLV_SENS_DATA_18,
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// AGB0_REG_EXT_SLV_SENS_DATA_19,
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// AGB0_REG_EXT_SLV_SENS_DATA_20,
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// AGB0_REG_EXT_SLV_SENS_DATA_21,
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// AGB0_REG_EXT_SLV_SENS_DATA_22,
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// AGB0_REG_EXT_SLV_SENS_DATA_23,
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// // Break
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// AGB0_REG_FIFO_EN_1 = 0x66,
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// AGB0_REG_FIFO_EN_2,
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// AGB0_REG_FIFO_MODE,
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// // Break
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// AGB0_REG_FIFO_COUNT_H = 0x70,
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// AGB0_REG_FIFO_COUNT_L,
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// AGB0_REG_FIFO_R_W,
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// // Break
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// AGB0_REG_DATA_RDY_STATUS = 0x74,
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// // Break
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// AGB0_REG_FIFO_CFG = 0x76,
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// // Break
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// AGB0_REG_MEM_START_ADDR = 0x7C, // Hmm, Invensense thought they were sneaky not listing these locations on the datasheet...
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// AGB0_REG_MEM_R_W = 0x7D, // These three locations seem to be able to access some memory within the device
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// AGB0_REG_MEM_BANK_SEL = 0x7E, // And that location is also where the DMP image gets loaded
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// AGB0_REG_REG_BANK_SEL = 0x7F,
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// // Bank 1
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// AGB1_REG_SELF_TEST_X_GYRO = 0x02,
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// AGB1_REG_SELF_TEST_Y_GYRO,
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// AGB1_REG_SELF_TEST_Z_GYRO,
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// // Break
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// AGB1_REG_SELF_TEST_X_ACCEL = 0x0E,
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// AGB1_REG_SELF_TEST_Y_ACCEL,
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// AGB1_REG_SELF_TEST_Z_ACCEL,
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// // Break
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// AGB1_REG_XA_OFFS_H = 0x14,
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// AGB1_REG_XA_OFFS_L,
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// // Break
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// AGB1_REG_YA_OFFS_H = 0x17,
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// AGB1_REG_YA_OFFS_L,
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// // Break
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// AGB1_REG_ZA_OFFS_H = 0x1A,
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// AGB1_REG_ZA_OFFS_L,
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// // Break
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// AGB1_REG_TIMEBASE_CORRECTION_PLL = 0x28,
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// // Break
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// AGB1_REG_REG_BANK_SEL = 0x7F,
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// // Bank 2
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// AGB2_REG_GYRO_SMPLRT_DIV = 0x00,
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/*
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Gyro sample rate divider. Divides the internal sample rate to generate the sample
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rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate.
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NOTE: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and
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(0 < DLPF_CFG < 7).
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ODR is computed as follows:
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1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])
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*/
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// AGB2_REG_GYRO_CONFIG_1,
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typedef enum{ // Full scale range options in degrees per second
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dps250 = 0x00,
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dps500,
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dps1000,
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dps2000,
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}ICM_20948_GYRO_CONFIG_1_FS_SEL_e;
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typedef enum{ // Format is dAbwB_nXbwZ - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
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gyr_d196bw6_n229bw8 = 0x00,
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gyr_d151bw8_n187bw6,
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gyr_d119bw5_n154bw3,
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gyr_d51bw2_n73bw3,
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gyr_d23bw9_n35bw9,
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gyr_d11bw6_n17bw8,
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gyr_d5bw7_n8bw9,
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gyr_d361bw4_n376bw5,
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}ICM_20948_GYRO_CONFIG_1_DLPCFG_e;
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// AGB2_REG_GYRO_CONFIG_2,
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// AGB2_REG_XG_OFFS_USRH,
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// AGB2_REG_XG_OFFS_USRL,
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// AGB2_REG_YG_OFFS_USRH,
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// AGB2_REG_YG_OFFS_USRL,
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// AGB2_REG_ZG_OFFS_USRH,
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// AGB2_REG_ZG_OFFS_USRL,
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// AGB2_REG_ODR_ALIGN_EN,
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// // Break
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// AGB2_REG_ACCEL_SMPLRT_DIV_1 = 0x10,
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// AGB2_REG_ACCEL_SMPLRT_DIV_2,
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// AGB2_REG_ACCEL_INTEL_CTRL,
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// AGB2_REG_ACCEL_WOM_THR,
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// AGB2_REG_ACCEL_CONFIG,
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typedef enum{
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gpm2 = 0x00,
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gpm4,
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gpm8,
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gpm16,
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}ICM_20948_ACCEL_CONFIG_FS_SEL_e;
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typedef enum{ // Format is dAbwB_nXbwZ - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
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acc_d246bw_n265bw = 0x00,
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acc_d246bw_n265bw_1,
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acc_d111bw4_n136bw,
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acc_d50bw4_n68bw8,
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acc_d23bw9_n34bw4,
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acc_d11bw5_n17bw,
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acc_d5bw7_n8bw3,
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acc_d473bw_n499bw,
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}ICM_20948_ACCEL_CONFIG_DLPCFG_e;
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// AGB2_REG_ACCEL_CONFIG_2,
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// // Break
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// AGB2_REG_FSYNC_CONFIG = 0x52,
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// AGB2_REG_TEMP_CONFIG,
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// AGB2_REG_MOD_CTRL_USR,
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// // Break
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// AGB2_REG_REG_BANK_SEL = 0x7F,
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// // Bank 3
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// AGB3_REG_I2C_MST_ODR_CONFIG = 0x00,
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// AGB3_REG_I2C_MST_CTRL,
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// AGB3_REG_I2C_MST_DELAY_CTRL,
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// AGB3_REG_I2C_SLV0_ADDR,
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// AGB3_REG_I2C_SLV0_REG,
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// AGB3_REG_I2C_SLV0_CTRL,
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// AGB3_REG_I2C_SLV0_DO,
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// AGB3_REG_I2C_SLV1_ADDR,
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// AGB3_REG_I2C_SLV1_REG,
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// AGB3_REG_I2C_SLV1_CTRL,
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// AGB3_REG_I2C_SLV1_DO,
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// AGB3_REG_I2C_SLV2_ADDR,
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// AGB3_REG_I2C_SLV2_REG,
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// AGB3_REG_I2C_SLV2_CTRL,
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// AGB3_REG_I2C_SLV2_DO,
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// AGB3_REG_I2C_SLV3_ADDR,
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// AGB3_REG_I2C_SLV3_REG,
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// AGB3_REG_I2C_SLV3_CTRL,
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// AGB3_REG_I2C_SLV3_DO,
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// AGB3_REG_I2C_SLV4_ADDR,
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// AGB3_REG_I2C_SLV4_REG,
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// AGB3_REG_I2C_SLV4_CTRL,
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// AGB3_REG_I2C_SLV4_DO,
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// AGB3_REG_I2C_SLV4_DI,
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// // Break
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// AGB3_REG_REG_BANK_SEL = 0x7F,
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// // Magnetometer
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// M_REG_WIA2 = 0x01,
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// // Break
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// M_REG_ST1 = 0x10,
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// M_REG_HXL,
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// M_REG_HXH,
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// M_REG_HYL,
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// M_REG_HYH,
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// M_REG_HZL,
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// M_REG_HZH,
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// M_REG_ST2,
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// // Break
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// M_REG_CNTL2 = 0x31,
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// M_REG_CNTL3,
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// M_REG_TS1,
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// M_REG_TS2,
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _ICM_20948_ENUMERATIONS_H_ */ |