186 lines
4.9 KiB
C
186 lines
4.9 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2009 Develer S.r.l. (http://www.develer.com/)
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* -->
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*
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* \brief I2S driver implementation.
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*
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* \author Luca Ottaviano <lottaviano@develer.com>
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*/
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/*
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* TODO: Revise the public api of this module to be more generic. Evalutate to
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* implement the more generic layer to be common to all I2S BeRTOS drivers.
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*/
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#include "i2s_at91.h"
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#include "cfg/cfg_i2s.h"
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// Define log settings for cfg/log.h.
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#define LOG_LEVEL I2S_LOG_LEVEL
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#define LOG_FORMAT I2S_LOG_FORMAT
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#include <cfg/log.h>
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#include <drv/timer.h>
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#include <io/arm.h>
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#define DATALEN (15 & SSC_DATLEN_MASK)
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// FIXME: this is not correct for 16 <= DATALEN < 24
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#define PDC_DIV ((DATALEN / 8) + 1)
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/*
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* PDC_DIV must be 1, 2 or 4, which are the bytes that are transferred
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* each time the PDC reads from memory.
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*/
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STATIC_ASSERT(PDC_DIV % 2 == 0);
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#define PDC_COUNT (CONFIG_PLAY_BUF_LEN / PDC_DIV)
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static uint8_t play_buf1[CONFIG_PLAY_BUF_LEN];
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static uint8_t play_buf2[CONFIG_PLAY_BUF_LEN];
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// the buffer in PDC next is play_buf2
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volatile bool is_second_buf_next;
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uint8_t *i2s_getBuffer(unsigned buf_num)
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{
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LOG_INFO("getBuffer start\n");
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if (i2s_isPlaying())
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{
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ASSERT(0);
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return 0;
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}
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if (buf_num == I2S_SECOND_BUF)
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return play_buf2;
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else if (buf_num == I2S_FIRST_BUF)
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return play_buf1;
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else
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return 0;
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}
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uint8_t *i2s_getFreeBuffer(void)
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{
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if (!i2s_isPlaying())
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{
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ASSERT(0);
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return 0;
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}
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// wait PDC transmission end
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if (!(SSC_SR & BV(SSC_ENDTX)))
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return 0;
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uint8_t *ret_buf = 0;
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// the last time we got called, the second buffer was in PDC next
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if (is_second_buf_next)
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{
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is_second_buf_next = false;
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ret_buf = play_buf1;
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}
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// the last time the first buffer was in PDC next
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else
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{
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is_second_buf_next = true;
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ret_buf = play_buf2;
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}
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if (ret_buf)
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{
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SSC_TNPR = (reg32_t) ret_buf;
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SSC_TNCR = PDC_COUNT;
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}
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return ret_buf;
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}
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bool i2s_start(void)
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{
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/* Some time must pass between disabling and enabling again the transmission
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* on SSC. A good empirical value seems >15 us. We try to avoid putting an
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* explicit delay, instead we disable the transmitter when a sound finishes
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* and hope that the delay has passed before we enter here again.
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*/
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SSC_CR = BV(SSC_TXDIS);
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timer_delay(10);
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SSC_PTCR = BV(PDC_TXTDIS);
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SSC_TPR = (reg32_t)play_buf1;
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SSC_TCR = PDC_COUNT;
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SSC_TNPR = (reg32_t)play_buf2;
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SSC_TNCR = PDC_COUNT;
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is_second_buf_next = true;
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SSC_PTCR = BV(PDC_TXTEN);
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/* enable output */
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SSC_CR = BV(SSC_TXEN);
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return true;
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}
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#define BITS_PER_CHANNEL 16
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#define N_OF_CHANNEL 2
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// TODO: check the computed value?
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/* The last parameter (2) is due to the hadware on at91sam7s. */
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#define MCK_DIV (CPU_FREQ / CONFIG_SAMPLE_FREQ / BITS_PER_CHANNEL / N_OF_CHANNEL / 2)
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#define CONFIG_DELAY 1
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#define CONFIG_PERIOD 15
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#define CONFIG_DATNB 1
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#define CONFIG_FSLEN 15
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#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
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#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
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#define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
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#define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
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#define SSC_DMA_IRQ_PRIORITY 5
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void i2s_init(void)
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{
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PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
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/* reset device */
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SSC_CR = BV(SSC_SWRST);
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SSC_CMR = MCK_DIV & SSC_DIV_MASK;
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SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
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SSC_TFMR = DATALEN | DATNB | FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
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/* Disable all irqs */
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SSC_IDR = 0xFFFFFFFF;
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/* Enable the SSC IRQ */
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AIC_IECR = BV(SSC_ID);
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/* enable i2s */
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PMC_PCER = BV(SSC_ID);
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/* Enable SSC */
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SSC_CR = BV(SSC_TXEN);
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}
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